Link utilization
∑
N A t
( )
t =1
LU =
, 0 ≤ LU ≤ 1
(6.8)
N
where:
⎧
i
t
1 If trafficpasses link in cycle
A t
( ) = ⎨
⎪
⎪ 0 If no trafficpasses link in n cycle
i
t
⎩
174
Network-on-Chip
supply voltage reduction magnifies the noise sensitivity of link circuitry. Since
a lower link frequency decreases the ratio of timing uncertainty to bit time, frequency reduction improves communication reliability. Bit error rate (BER) is a
measure of performance in link circuitry design. Link designs can achieve 10
−15
BER over a wide range of voltages (0.9–2.5 V) and frequencies (200–700 MHz). In
this work, it is assumed that within the range of multiple voltage and frequency
levels, link circuitry can always function above the noise margin and achieve
low BER. Due to the timing uncertainty, during frequency transition, when the
receiver is trying to lock in the input clock, link circuitry is disabled.
6.4.1.1 History-Based DVS
The policy controlling DVS links has to judiciously trade off power and performance, minimizing the power consumption of the network while maintaining high performance. We proposed a distributed history-based DVS policy,
where each router port predicts future communication workload based on the
analysis of prior traffic, and then dynamically adjusts the frequencies (and corresponding voltages) of its communication links to track network load.
6.4.1.1.1 Communication Traffic Characterization
Communication traffic characteristics can be captured with several potential
network measures. An obvious measure for DVS links is link utilization,
which is defined as follows:
N is the number of link clock cycles, which is sampled within a history
window size H defined in router clock cycles
Link utilization is a direct measure of traffic workload. A higher link utilization reflects that more data are sent to the next router. Assuming that history is predictive, a higher link frequency is needed to meet the performance
requirement. Conversely, lower link utilization implies the existence of more
idle cycles. Here, decreasing the link frequency can lead to power savings
without significantly hurting performance.