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Low-Power Techniques for Network-on-Chip
To investigate how predictive link utilization is of network load, the
utilization of a link within a two-dimensional (2D) 8  × 8 mesh network is
traced. At low traffic workloads, contention for buffers and links is rare. In
this case, link utilization is bounded by flit arrival rate that is slow at low
traffic workloads. As network traffic increases, more flits are relayed between
adjacent routers and the utilization of each corresponding link also increases.
When the network traffic approaches to the congestion point, resource contention results in flits being stalled in input buffers, since they can be relayed
to the next router only if free buffers are available. Limited available buffer
space in the succeeding router begins to be a tighter constraint, causing link
utilization to decrease. When the network is highly congested, inter-router
flit transmission is totally constrained by the availability of free buffers. Link
utilization thus starts to dip.
At low network loads, since the flit will not be stalled in the succeeding
router, any increase in link delay directly contributes to the overall packet
latency. At high network loads, flits will be stalled in the next router for a
long time anyway. Getting there faster will not help. In this case, link frequency can be decreased more aggressively with minimal delay overhead.
Hence, link utilization alone will not be sufficient for guiding the historybased DVS policy. The other two parameters—input buffer utilization and
input buffer age—need to be investigated.
Input buffer utilization
H
∑ [F t
( )/ B]
t =1
(6.9)
BU =
, 0 ≤ BU ≤ 1
H
where:
F(t) is the number of input buffers that are occupied at time t
B is the input buffer size
Input buffer age
H
D t
( )
∑ ∑ (t di − t ai )
t=1
i=1
BA =
(6.10)
∑
H D t
( )
t=1
where:
D(t) is the number of flits that leave the input buffer at cycle t of a history
interval H
t d is the departure time of flit i from this buffer
t a is the arrival time of flit i at the input buffer