172
Network-on-Chip
Power supply
V DD
V DDL
Link
SVS
Encoder
Decoder
Router
Router
V DD
Power supply
Figure 6.13
Low-swing signaling in NoC interconnect.
where SVS is used to supply the lower voltage (V DDL ) to the driver. Hence,
a high-to-low voltage level shifter is needed in the transmitting router as
shown in Section 6.2.3.1. Similarly, in the receiving router side, a low-to-high
voltage level shifter is an utmost requirement. The amount of energy saving
due to low-swing signaling is shown as follows:
E saving = E uncoded_link − (E codec + E coded_link )
(6.7)
6.4 System-Level Power Reduction
The total power consumption in a SoC is the combination of dynamic and
leakage power. For dynamic power reduction at system level, DVS/DFS is
very well known in VLSI community and also adopted in NoC design.
6.4.1 Dynamic Voltage Scaling
This section highlights the work cited by Shang et al. (2003) on DVS. Dynamic
power consumption can be reduced by lowering the supply voltage. This
requires reducing the clock frequency accordingly to compensate for the
additional gate delay due to the lower voltage. The basic idea is that because
of high variance in network traffic, when a link is underutilized, the link can
be slowed down without affecting performance.
A variable frequency link consists of the components of a typical high-speed
link: a transmitter to convert digital binary signals into electrical signals, a signaling channel, a receiver to convert electrical signals back to digital data, and
a clock recovery block to compensate for delay through the signaling channel.
In addition, it needs an adaptive power supply regulator that tracks the link
frequency, regulates the voltage to the minimum level required, and feeds the
regulated supply voltage to multiple links of a network channel, amortizing
Network-on-Chip
Power supply
V DD
V DDL
Link
SVS
Encoder
Decoder
Router
Router
V DD
Power supply
Figure 6.13
Low-swing signaling in NoC interconnect.
where SVS is used to supply the lower voltage (V DDL ) to the driver. Hence,
a high-to-low voltage level shifter is needed in the transmitting router as
shown in Section 6.2.3.1. Similarly, in the receiving router side, a low-to-high
voltage level shifter is an utmost requirement. The amount of energy saving
due to low-swing signaling is shown as follows:
E saving = E uncoded_link − (E codec + E coded_link )
(6.7)
6.4 System-Level Power Reduction
The total power consumption in a SoC is the combination of dynamic and
leakage power. For dynamic power reduction at system level, DVS/DFS is
very well known in VLSI community and also adopted in NoC design.
6.4.1 Dynamic Voltage Scaling
This section highlights the work cited by Shang et al. (2003) on DVS. Dynamic
power consumption can be reduced by lowering the supply voltage. This
requires reducing the clock frequency accordingly to compensate for the
additional gate delay due to the lower voltage. The basic idea is that because
of high variance in network traffic, when a link is underutilized, the link can
be slowed down without affecting performance.
A variable frequency link consists of the components of a typical high-speed
link: a transmitter to convert digital binary signals into electrical signals, a signaling channel, a receiver to convert electrical signals back to digital data, and
a clock recovery block to compensate for delay through the signaling channel.
In addition, it needs an adaptive power supply regulator that tracks the link
frequency, regulates the voltage to the minimum level required, and feeds the
regulated supply voltage to multiple links of a network channel, amortizing