170
Network-on-Chip
TABLe 6.2
Binary and Gray Coding Scheme for 4-bit Address Bus
Time→
Time→
D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
(Binary Sequence)
(Gray Sequence)
Deogun et al. (2004) proposed an encoding scheme that also tackles the rising runtime leakage power levels in such buses along with cross talk and
dynamic power. They introduced a new buffer design approach with selective use of high-threshold voltage transistors and coupled this buffer design
with a novel bus encoding scheme. For any LPC scheme, a trade-off analysis
has to be performed between bus energy reduction and the amount of extra
energy consumed by the codec. For technologies such as 90 nm or above,
Sridhara and Shanbhag (2005) showed that codec overhead is more in BI
scheme than in bus energy saving, but this trade-off will be increasingly
favorable in future technologies.
Generally, an address bus will tend to have a sequential behavior; hence, a
gray coding scheme is perfect for an address bus where only one transition
is occurred per time slot. In actual design, it is always advisable to implement the gray counter from its finite state machine. Table 6.2 presents both
binary and gray sequences for an address bus. Although a sequential value
on the address bus is generally too simplistic, for a real system only some
percentage of bus addresses are typically sequential with the others being
essentially random. In such case, a mixed coding, gray and BI coding, will
give the best results for both peak and average power dissipation in the bus.
6.3.3 On-Chip Serialization
Bus encoding techniques enlarge the physical transfer unit in NoC. Large
physical transfer unit increases the network area and energy consumption,
especially for switching circuit and buffering units in switch fabrics. On-chip
serializer and deserializer can be used to reduce the physical transfer unit size
and further reduce the area and energy consumption of the switch fabric. It
reduces the overall network area and optimizes power consumption, which
is well explained in the work of Lee et al. (2004, 2005). The power consumption decreases with the increasing ratio of serializer under low frequency.
Unfortunately, with the increasing ratio of serialization under higher frequency,
the power consumption increases because of large driver to provide high driving ability. Huang et al. (2008) observed that a 4:1 serializer is an optimized
ratio to achieve energy saving. Chuang et al. (2008) implemented the serializer