⎡
dV 1
dV 2 ⎤ V 1
f
V 1
i
C s × ( + λ)×
− ×
=
−
⎣ ⎢ 1
dt
λ dt ⎦ ⎥ R 1 R 1
⎡
dV k−1
dV k
dV k+1 ⎤
C s × − ×
+ 1 + 2λ) ×
− ×
λ
(
λ
⎣ ⎢
dt
dt
dt ⎦ ⎥
V k
f
V k
i
=
−
, , where k = , , ,…, (n − )
2 3 4
1
R k R k
167
Low-Power Techniques for Network-on-Chip
6.3.1 Bus energy Model
In on-chip interconnect, lines are assumed to be distributed, lossy, and
capacitively and inductively coupled. The energy model of such interconnect
is described in the work of Sotiriadis and Chandrakasan (2002). The effect of
inductance (L) can be neglected if f << R/(2πL) (where f is the frequency and R
denotes the bus resistance), which is true in most NoC interconnects. Thus,
NoC interconnect in DSM era can be modeled as resistance-capacitance
network (Benini and Micheli 2006). The model of an n-wire interconnect in
parallel is shown in Figure 6.10. In the figure, C s and C c are the substrate and
coupling capacitances, respectively; R i represents the on–off resistance of the
ith driver; V j
i and V j
f denote the initial and final voltages, respectively, in the
jth interconnect. The ratio of coupling capacitance to substrate capacitance
is denoted as λ (λ = C c /C s ). It is a technology parameter and increases with
shrinking technology feature size.
Sotiriadis and Chandrakasan (2000) proposed a three-wire bus energy
model. The proposed bus energy model is presented below. Using Kirchoff’s
current law, the current (I) equation of each line is
V 1
f
V 1
i
V 2
i
R 1
R 2
R 3
C C
C C
C C
C C
C S
C S
C S
C S
R n
V 2
f
V 3
f
V n
f
V 3
i
V n
i
Figure 6.10
DSM model of n interconnects.