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Network-on-Chip
after wake time, it needs some cycles to go to the active state, which causes
performance penalty. Power gating can be applied to circuit blocks with
various granularities. Depending on the granularity of target circuit blocks
(i.e., power domains), the power gating is classified into coarse-grained and
fine-grained approaches.
In fine-grain power gating, the switch is placed locally inside each standard
cell. Since the switch must supply the worst-case current required by the cell,
it has to be quite large in order not to impact performance. This approach has
received a lot of attention in recent years because of its flexibility and short
wake-up latency. In coarse-grain power gating, a block of gates has its power
switched by a collection of switch cells. The sizing of a coarse-grain switch
network is more difficult than that of a fine-grain switch network as the exact
switching activity of the logic it supplies is not known and can only be estimated. But coarse-grain gating designs have significantly less area penalty
than fine-grain gating designs. Each target circuit block is surrounded by a
power/ground ring. Power switches are inserted between the core ring and the
power/ground IO cells. The power supply to the circuit block can be controlled
by the power switches. Since the power supply to all cells inside the core ring
is controlled at one time, this approach is well suited to the IP- or module-level
power management. The coarse-grained approach has been popularly used,
since its IP- or module-level power management is straightforward and easy to
control. However, it typically imposes a microsecond order wake-up latency.
The implementation of power gating presents certain challenges to the
designer. which include the following:
1. Design of power switching fabric
2. Design of power gating controller
3. Selection and use of retention registers and isolation cells
4. Minimization of the impact of power gating on timing and area
5. The functional control of clocks and resets
6. Interface isolation
7. Constraint development for implementation and analysis
6.3 Standard Low-Power Methods for NoC Links
There are a number of power reduction techniques for interconnects that
have been widely used in VLSI design and also adopted in NoC. This section
gives an overview of the following methods: (1) low-power coding (LPC),
(2) on-chip serialization, and (3) low-power signaling. First, we will start
with bus energy model as described in Section 6.3.1.
Network-on-Chip
after wake time, it needs some cycles to go to the active state, which causes
performance penalty. Power gating can be applied to circuit blocks with
various granularities. Depending on the granularity of target circuit blocks
(i.e., power domains), the power gating is classified into coarse-grained and
fine-grained approaches.
In fine-grain power gating, the switch is placed locally inside each standard
cell. Since the switch must supply the worst-case current required by the cell,
it has to be quite large in order not to impact performance. This approach has
received a lot of attention in recent years because of its flexibility and short
wake-up latency. In coarse-grain power gating, a block of gates has its power
switched by a collection of switch cells. The sizing of a coarse-grain switch
network is more difficult than that of a fine-grain switch network as the exact
switching activity of the logic it supplies is not known and can only be estimated. But coarse-grain gating designs have significantly less area penalty
than fine-grain gating designs. Each target circuit block is surrounded by a
power/ground ring. Power switches are inserted between the core ring and the
power/ground IO cells. The power supply to the circuit block can be controlled
by the power switches. Since the power supply to all cells inside the core ring
is controlled at one time, this approach is well suited to the IP- or module-level
power management. The coarse-grained approach has been popularly used,
since its IP- or module-level power management is straightforward and easy to
control. However, it typically imposes a microsecond order wake-up latency.
The implementation of power gating presents certain challenges to the
designer. which include the following:
1. Design of power switching fabric
2. Design of power gating controller
3. Selection and use of retention registers and isolation cells
4. Minimization of the impact of power gating on timing and area
5. The functional control of clocks and resets
6. Interface isolation
7. Constraint development for implementation and analysis
6.3 Standard Low-Power Methods for NoC Links
There are a number of power reduction techniques for interconnects that
have been widely used in VLSI design and also adopted in NoC. This section
gives an overview of the following methods: (1) low-power coding (LPC),
(2) on-chip serialization, and (3) low-power signaling. First, we will start
with bus energy model as described in Section 6.3.1.