6
Low-Power Techniques
for Network-on-Chip
6.1 Introduction
As the number of processing elements keeps on increasing in network-onchip (NoC), power consumption is one of the major concerns in designing such systems since it affects their battery life and packaging costs for
heat dissipation. The increasing power density not only raises packaging
and cooling challenges, but also enhances reliability problems as the mean
time between failures (MTBF) decreases exponentially with temperature. In
addition, timing requirement degrades and leakage current increases with
temperature. Since last decade power consumption has not been a primary
concern in chip design, while the cost, area, and timing issues were mostly
being addressed by the designers. Today, in ultra-deep submicron (UDSM)
technology, the power budget is one of the important goals for most systemon-chip (SoC) designs. Exceeding the power budget will increase the packaging cost, thermal design, and regulator design, and will also affect the
timing, reliability, and battery life.
As power minimization is one of the major design challenges, this chapter
addresses different low-power techniques that have been adopted in the NoC
paradigm. The rest of the chapter has been organized as follows: this section
briefly discusses about the different power components. Sections 6.2 and 6.3
discuss about the standard low-power methods for NoC routers and links,
respectively. Section 6.4 describes the different system-level power reduction
techniques such as dynamic voltage scaling (DVS), dynamic frequency scaling (DFS), voltage–frequency island (VFI) partitioning, and runtime power
gating. Finally, Section 6.5 summarizes the chapter.
Total chip power consumption can be split into dynamic power, leakage
power, interconnect power, and IO power. The two components that constitute dynamic power consumption are switching power and internal power.
The switching power consumption can be described as
P sw = α × C L ×V swing ×V DD × f clock
(6.1)
155
Low-Power Techniques
for Network-on-Chip
6.1 Introduction
As the number of processing elements keeps on increasing in network-onchip (NoC), power consumption is one of the major concerns in designing such systems since it affects their battery life and packaging costs for
heat dissipation. The increasing power density not only raises packaging
and cooling challenges, but also enhances reliability problems as the mean
time between failures (MTBF) decreases exponentially with temperature. In
addition, timing requirement degrades and leakage current increases with
temperature. Since last decade power consumption has not been a primary
concern in chip design, while the cost, area, and timing issues were mostly
being addressed by the designers. Today, in ultra-deep submicron (UDSM)
technology, the power budget is one of the important goals for most systemon-chip (SoC) designs. Exceeding the power budget will increase the packaging cost, thermal design, and regulator design, and will also affect the
timing, reliability, and battery life.
As power minimization is one of the major design challenges, this chapter
addresses different low-power techniques that have been adopted in the NoC
paradigm. The rest of the chapter has been organized as follows: this section
briefly discusses about the different power components. Sections 6.2 and 6.3
discuss about the standard low-power methods for NoC routers and links,
respectively. Section 6.4 describes the different system-level power reduction
techniques such as dynamic voltage scaling (DVS), dynamic frequency scaling (DFS), voltage–frequency island (VFI) partitioning, and runtime power
gating. Finally, Section 6.5 summarizes the chapter.
Total chip power consumption can be split into dynamic power, leakage
power, interconnect power, and IO power. The two components that constitute dynamic power consumption are switching power and internal power.
The switching power consumption can be described as
P sw = α × C L ×V swing ×V DD × f clock
(6.1)
155