154
Network-on-Chip
Srinivasan, K., and Chatha, K. S. 2005. A technique for low energy mapping and
routing in network-on-chip architecture. IEEE International Symposiun on Low
Power Electronics and Design, IEEE Press, pp. 387–392.
Srinivasan, K., Chatha, K. S., and Konjevod, G. 2006. Linear-programming-based
techniques for synthesis of network-on-chip architectures. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 14, no. 4, pp. 407–420.
Tavanpour, M., Khademzadeh, A., and Janidarmian, M. 2009. Chain-mapping for
mesh based network-on-chip architecture. IEICE Electronics Express, vol. 6,
no. 22, pp. 1535–1541.
Tavanpour, M., Khademzadeh, A., Pourkiani, S., and Yaghobi, M. 2010. GBMAP: An
evolutionary approach to mapping cores onto a mesh-based NoC architecture.
Journal of Communication and Computer, vol. 7, no. 3, pp. 1–7.
Tornero, R., Sterrantino, V., Palesi, M., and Orduna, J. 2009. A multi-objective strategy for concurrent mapping and routing in networks on chip. IEEE International
Symposium on Parallel and Distributed Processing, IEEE Press, pp. 1–8.
Tosun, S. 2011a. Clustered-based application mapping method for network-on-chip.
Journal of Advances in Engineering Software vol. 42, no. 10, pp. 868–874.
Tosun, S. 2011b. New heuristic algorithm for energy aware application mapping and
routing on mesh-based NoCs. Journal of System Architecture, vol. 57, pp. 69–78.
Tosun, S., Ozturk, O., and Ozen, M. 2009. An ILP formulation for application mapping onto network-on-chips. International Conference on Application of Information
and Communication Technologies, IEEE Press, pp. 1–5.
Wang, J., Li, Y., Chai, S., and Peng, Q. 2011. Bandwidth-aware application mapping
for NoC-based MPSoCs. Journal of Computational Information Systems, vol. 7,
no. 1, pp. 152–159.
Wang, K., Huang, L., Zhou, C., and Pang, W. 2003. Particle swarm optimization for
traveling salesman problem. Proceedings of the Second International Conference on
Machine Learning and Cybernetics, IEEE Press, pp. 1583–1585.
Wang, X., Yang, M., Jiang, Y., and Liu, P. 2009. Power-aware mapping for networkon-chip architectures under bandwidth and latency constraints. International
Conference on Embedded and Multimedia Computing, IEEE Press, pp. 1–6.
Wang, X., Yang, M., Jiang, Y., and Liu, P. 2010. Power-aware mapping approach to map
IP cores onto NoCs under bandwidth and latency constraints. ACM Transactions
on Architecture and Code Optimization, vol. 7, no. 1, pp. 1–30.
Yang, B., Guang, L., Xu, T. C., Santti, T., and Plosila, J. 2010a. Multi-application mapping algorithm for network-on-chip platforms. IEEE 26th Convention of Electrical
and Electronics Engineers in Israel, IEEE Press, pp. 540–544.
Yang, B., Xu, T. C., Santti, T., and Plosila, J. 2010b. Tree-model based mapping for
energy-efficient and low-latency network-on-chip. International Symposium on
Design and Diagnostics of Electronics Circuits and Systems, IEEE Press, pp. 189–192.
Yu, M. Y., Li, M., Song, J. J., Fu, F. F., and Bai, Y. X. 2009. Pipelining-based high throughput low energy mapping on network-on-chip. Euromicro International Conference
on Digital System Design/Architectures, Methods and Tools, IEEE Press, pp. 427–432.
Zhou, W., Zhang, Y., and Mao, Z. 2006. An application specific NoC mapping for optimized delay. IEEE International Conference on Design and Test of Integrated Systems
in Nanoscale, IEEE Press, pp. 184–188.
Zhou, W., Zhang, Y., and Mao, Z. 2007. Link-load balance aware mapping and routing
for NoC. WSEAS Transactions on Circuits and Systems, vol. 6, no. 11, pp. 583–591.
Network-on-Chip
Srinivasan, K., and Chatha, K. S. 2005. A technique for low energy mapping and
routing in network-on-chip architecture. IEEE International Symposiun on Low
Power Electronics and Design, IEEE Press, pp. 387–392.
Srinivasan, K., Chatha, K. S., and Konjevod, G. 2006. Linear-programming-based
techniques for synthesis of network-on-chip architectures. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 14, no. 4, pp. 407–420.
Tavanpour, M., Khademzadeh, A., and Janidarmian, M. 2009. Chain-mapping for
mesh based network-on-chip architecture. IEICE Electronics Express, vol. 6,
no. 22, pp. 1535–1541.
Tavanpour, M., Khademzadeh, A., Pourkiani, S., and Yaghobi, M. 2010. GBMAP: An
evolutionary approach to mapping cores onto a mesh-based NoC architecture.
Journal of Communication and Computer, vol. 7, no. 3, pp. 1–7.
Tornero, R., Sterrantino, V., Palesi, M., and Orduna, J. 2009. A multi-objective strategy for concurrent mapping and routing in networks on chip. IEEE International
Symposium on Parallel and Distributed Processing, IEEE Press, pp. 1–8.
Tosun, S. 2011a. Clustered-based application mapping method for network-on-chip.
Journal of Advances in Engineering Software vol. 42, no. 10, pp. 868–874.
Tosun, S. 2011b. New heuristic algorithm for energy aware application mapping and
routing on mesh-based NoCs. Journal of System Architecture, vol. 57, pp. 69–78.
Tosun, S., Ozturk, O., and Ozen, M. 2009. An ILP formulation for application mapping onto network-on-chips. International Conference on Application of Information
and Communication Technologies, IEEE Press, pp. 1–5.
Wang, J., Li, Y., Chai, S., and Peng, Q. 2011. Bandwidth-aware application mapping
for NoC-based MPSoCs. Journal of Computational Information Systems, vol. 7,
no. 1, pp. 152–159.
Wang, K., Huang, L., Zhou, C., and Pang, W. 2003. Particle swarm optimization for
traveling salesman problem. Proceedings of the Second International Conference on
Machine Learning and Cybernetics, IEEE Press, pp. 1583–1585.
Wang, X., Yang, M., Jiang, Y., and Liu, P. 2009. Power-aware mapping for networkon-chip architectures under bandwidth and latency constraints. International
Conference on Embedded and Multimedia Computing, IEEE Press, pp. 1–6.
Wang, X., Yang, M., Jiang, Y., and Liu, P. 2010. Power-aware mapping approach to map
IP cores onto NoCs under bandwidth and latency constraints. ACM Transactions
on Architecture and Code Optimization, vol. 7, no. 1, pp. 1–30.
Yang, B., Guang, L., Xu, T. C., Santti, T., and Plosila, J. 2010a. Multi-application mapping algorithm for network-on-chip platforms. IEEE 26th Convention of Electrical
and Electronics Engineers in Israel, IEEE Press, pp. 540–544.
Yang, B., Xu, T. C., Santti, T., and Plosila, J. 2010b. Tree-model based mapping for
energy-efficient and low-latency network-on-chip. International Symposium on
Design and Diagnostics of Electronics Circuits and Systems, IEEE Press, pp. 189–192.
Yu, M. Y., Li, M., Song, J. J., Fu, F. F., and Bai, Y. X. 2009. Pipelining-based high throughput low energy mapping on network-on-chip. Euromicro International Conference
on Digital System Design/Architectures, Methods and Tools, IEEE Press, pp. 427–432.
Zhou, W., Zhang, Y., and Mao, Z. 2006. An application specific NoC mapping for optimized delay. IEEE International Conference on Design and Test of Integrated Systems
in Nanoscale, IEEE Press, pp. 184–188.
Zhou, W., Zhang, Y., and Mao, Z. 2007. Link-load balance aware mapping and routing
for NoC. WSEAS Transactions on Circuits and Systems, vol. 6, no. 11, pp. 583–591.