117
Evaluation of Network-on-Chip Architectures
Hu, J. and Marculescu, R. 2004. DyAD-smart routing for networks-on-chip. Proceedings
of Design and Automation Conference, pp. 260–263, July 7–11, San Diego, CA.
Kumar, A., Kundu, P., Singh, A. P., Peh, L. S., and Jha, N. K. 2007. A 4.6Tbits/s 3.6GHz
single-cycle NoC router with a novel switch allocator in 65nm CMOS. Proceedings
of IEEE International Conference on Computer Design, pp. 63–70, October 7–10,
Lake Tahoe, CA.
Kundu, S., Soumya, J., and Chattopadhyay, S. 2012. Design and evaluation of meshof-tree based network-on-chip using virtual channel router. Microprocessors and
Microsystems Journal, vol. 36, pp. 471–488.
Marculescu, R., Ogras, U. Y., Peh, L. S., Jerger, N. E., and Hoskote, Y. 2009. Outstanding
research problems in NoC design: Systems, microarchitecture, and circuit perspectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 28, no. 1, pp. 3–21.
Millberg, M., Nilsson, E., Thid, R., and Jantsch, A. 2004. Guaranteed bandwidth using
looped containers in temporally disjoint networks within the Nostrum network
on chip. Proceedings of IEEE Design, Automation, and Test in Europe, pp. 890–895,
February 16–20, Paris, France.
Ogras, U. Y., Hu, J., and Marculescu, R. 2005. Key research problems in NoC design:
A holistic perspective. Proceedings of IEEE/ACM/IFIP International Conference on
Hardware/Software Codesign and System Synthesis, pp. 69–74, September, Jersey
City, NJ.
Pande, P. P., Grecu, C., Ivanov, A., and Saleh, R. 2003. High-throughput switch-based
interconnect for future SoCs. Proceedings of IEEE International Workshop on
System-on-Chip for Real Time Applications, pp. 304–310, June 30-July 2, Alberta,
Canada.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for MP-SOC interconnect architectures. IEEE
Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, August.
Park, K. and Willinger, W. 2000. Self-Similar Network Traffic and Performance Evaluation.
Wiley, New York.
Pavlidis, V. F. and Friedman, E. G. 2007. 3-D Topologies for networks-on-chip. IEEE
Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090.
Rijpkema, E., Goossens, K. G. W., and Radulescu, A. 2003. Trade offs in the design
of a router with both guaranteed and best-effort services for network on chip
(extended version). IEE Proceedings of Computers and Digital Techniques, vol. 150,
no. 5, pp. 294–302.
Salminen, E., Kulmala, A., and Hamalainen, T. D. 2008. Survey of network-on-chip
proposals. White Paper,
© OCP-IP.
Soteriou, V., Eisley, N., Wang, H., Li, B., and Peh, L. S. 2007. Polaris: A system-level
roadmap for on-chip interconnection networks. IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol. 15, no. 8, pp. 855–868.
Sotiriadis, P. P. and Chandrakasan, A. P. 2002. A bus energy model for deep submicron
technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 10, no. 3, pp. 341–350.
Synopsys. 2006. Synopsys Prime Power Manual. Version Y-2006.06. http://www.synopsys
.com/Support/LI/Installation/Documents/Archive/iugux_y2006_06.pdf.
Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D. et al.
2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE Journal
of Solid-State Circuits, vol. 43, no. 1, pp. 29–41.
Evaluation of Network-on-Chip Architectures
Hu, J. and Marculescu, R. 2004. DyAD-smart routing for networks-on-chip. Proceedings
of Design and Automation Conference, pp. 260–263, July 7–11, San Diego, CA.
Kumar, A., Kundu, P., Singh, A. P., Peh, L. S., and Jha, N. K. 2007. A 4.6Tbits/s 3.6GHz
single-cycle NoC router with a novel switch allocator in 65nm CMOS. Proceedings
of IEEE International Conference on Computer Design, pp. 63–70, October 7–10,
Lake Tahoe, CA.
Kundu, S., Soumya, J., and Chattopadhyay, S. 2012. Design and evaluation of meshof-tree based network-on-chip using virtual channel router. Microprocessors and
Microsystems Journal, vol. 36, pp. 471–488.
Marculescu, R., Ogras, U. Y., Peh, L. S., Jerger, N. E., and Hoskote, Y. 2009. Outstanding
research problems in NoC design: Systems, microarchitecture, and circuit perspectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, vol. 28, no. 1, pp. 3–21.
Millberg, M., Nilsson, E., Thid, R., and Jantsch, A. 2004. Guaranteed bandwidth using
looped containers in temporally disjoint networks within the Nostrum network
on chip. Proceedings of IEEE Design, Automation, and Test in Europe, pp. 890–895,
February 16–20, Paris, France.
Ogras, U. Y., Hu, J., and Marculescu, R. 2005. Key research problems in NoC design:
A holistic perspective. Proceedings of IEEE/ACM/IFIP International Conference on
Hardware/Software Codesign and System Synthesis, pp. 69–74, September, Jersey
City, NJ.
Pande, P. P., Grecu, C., Ivanov, A., and Saleh, R. 2003. High-throughput switch-based
interconnect for future SoCs. Proceedings of IEEE International Workshop on
System-on-Chip for Real Time Applications, pp. 304–310, June 30-July 2, Alberta,
Canada.
Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for MP-SOC interconnect architectures. IEEE
Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, August.
Park, K. and Willinger, W. 2000. Self-Similar Network Traffic and Performance Evaluation.
Wiley, New York.
Pavlidis, V. F. and Friedman, E. G. 2007. 3-D Topologies for networks-on-chip. IEEE
Transactions on VLSI Systems, vol. 15, no. 10, pp. 1081–1090.
Rijpkema, E., Goossens, K. G. W., and Radulescu, A. 2003. Trade offs in the design
of a router with both guaranteed and best-effort services for network on chip
(extended version). IEE Proceedings of Computers and Digital Techniques, vol. 150,
no. 5, pp. 294–302.
Salminen, E., Kulmala, A., and Hamalainen, T. D. 2008. Survey of network-on-chip
proposals. White Paper,
© OCP-IP.
Soteriou, V., Eisley, N., Wang, H., Li, B., and Peh, L. S. 2007. Polaris: A system-level
roadmap for on-chip interconnection networks. IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol. 15, no. 8, pp. 855–868.
Sotiriadis, P. P. and Chandrakasan, A. P. 2002. A bus energy model for deep submicron
technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 10, no. 3, pp. 341–350.
Synopsys. 2006. Synopsys Prime Power Manual. Version Y-2006.06. http://www.synopsys
.com/Support/LI/Installation/Documents/Archive/iugux_y2006_06.pdf.
Vangal, S. R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D. et al.
2008. An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE Journal
of Solid-State Circuits, vol. 43, no. 1, pp. 29–41.