116
Network-on-Chip
the best in terms of performance for both WH and VC router-based NoCs.
This evaluation corresponds to self-similar traffic with varying locality factors. In terms of per packet energy consumption and area overhead, the WH
router-based MoT network ranks second in the list, next to the mesh structure that connects two cores to each router. With VC router, MoT consumes
lesser average packet energy than the mesh network that connects single
core to each router and occupies almost similar area such as mesh network
connecting single core to each router. The comparative study shows that
MoT-based NoC also works fine under application-specific traffic. On the
architecture front of WH and VC routers, due to lesser connectivity of MoT
routers, synthesis result shows that they can be operated at a higher frequency compared to other network structures, thus increasing the speed of
the overall network. However, for a system having large number of cores,
it can be predicted that MoTs will suffer in both energy and latency fronts
mainly due to the large number of pipelining stages required for the longer
edges. In BFT networks, this problem is much more severe as they require
more number of long edges as shown in Table 4.14. The upcoming trends
such as current mode signaling in NoC link and 3D NoC are expected to
alleviate this bottleneck, making MoT a more acceptable topology for larger
core-based NoC design.
Although in investigating the promise of any topology in a NoC paradigm,
applying self-similar traffic is expected to produce the average behavior of
the network, Chapter 5 will focus on a different application mapping algorithm in NoC paradigm and also evaluate the performance and cost of each
network under consideration under a set of real benchmark applications.
References
Bashirullah, R., Liu, W., and Cavin, R. K. 2003. Current-mode signaling in deep submicrometer global interconnects. IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol. 11, no. 3, pp. 406–417.
Bertozzi, D. and Benini, L. 2004. Xpipes: A network-on-chip architecture for gigascale
systems-on-chip. IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18–31.
Chi, H. C. and Chen, J. H. 2004. Design and implementation of a routing switch
for on-chip interconnection networks. Proceedings of Asia-Pacific Conference on
Advanced System Integrated Circuits, pp. 392–395, August 4–5, Fukuoka, Japan.
Decina, M., Trecordi, V., and Zanolini, G. 1991. Throughput and packet loss in deflection routing multichannel-metropolitan area networks. IEEE GLOBECOM,
pp. 1200–1208, December 2–5, Phoenix, AZ.
Duato, J., Yalamanchili, S., and Ni, L. 2003. Interconnection Networks: An Engineering
Approach. Morgan Kaufmann Publishers, San Francisco, CA.
Feero, B. S. and Pande, P. P. 2009. Networks-on-chip in a three dimensional environment:
A performance evaluation. IEEE Transactions on Computers, vol. 58, no. 1, pp. 32–45.
