0 . 0 0 2
0 . 0 0 4
0 . 0 0 6
0 . 0 0 8
0 . 0 1 0
0 . 0 1 2
0 . 0 1 4
0 . 0 1 6
0 . 0 1 8
0 . 0 2 0
240
Energy consumption (μJ)
200
160
120
80
40
Network
Router
Link
0
Offered load (packets/cycle/IP)
91
Evaluation of Network-on-Chip Architectures
that FIFO at the input channel has depth i and that at the output channel has
depth j, where j = 0 signifies that no FIFO is present at the output channel. In
this study, FIFO Depth 6–6 (FIFO depths at both the input and output channels are 6) has been taken as the reference. When contention occurs, FIFO at
the input channel allows some more data flits to make progress even though
the output channel is not available. However, FIFO at the output channel
allows a few flits to cross the crossbar even when the FIFO of the next router’s
input channel is full. Thus, decreasing the depth of any of the FIFOs will
generate FULL signal more frequently and thus have a negative impact on
performance. This is readily reflected in Table 4.4, as performance degrades
with decreasing FIFO depth.
Table 4.4 shows that the elimination of output channel FIFO in the MoT
router has very little impact on throughput and latency. In this case, the
number of flits stored in the router data path is lesser than that in reference
case (FIFO Depth 6–6) by 6. However, after getting the grant signal from any
output channel, header passes directly to the next router, saving one cycle
delay of FIFO at the output channel. This diminishes the negative impact of
eliminating FIFO at the output channel to some extent.
Network energy consumption also decreases with reducing the total FIFO
size of the router. From Table 4.4, it can be concluded that the elimination of the
output buffer reduces the energy consumption significantly at the cost marginal performance degradation. Therefore, to optimize the performance and
energy consumption, the WH router is modified by eliminating FIFO at the
output channel (FIFO Depth 6–0). This modified router architecture is used in
rest of the chapter. The modified router architecture has only two-cycle latency,
one cycle each in FIFO at the input channel and arbiter. The energy consumption profile of the MoT-based network after elimination of FIFO at the output
channel with uniformly distributed offered load is shown in Figure 4.14.
Figure 4.14
Network energy consumption in MoT with modified router under uniformly distributed
offered load.