8. Testing of Network-on-Chip Architectures.......................................... 235

8.1 Introduction ....................................................................................... 235

8.2 Testing Communication Fabric ....................................................... 236

8.2.1 Testing NoC Links ............................................................... 237

8.2.2 Testing NoC Switches.......................................................... 238

8.2.3 Test Data Transport ............................................................. 239

8.2.4 Test Transport Time Minimization—A Graph
Theoretic Formulation......................................................... 241

8.2.4.1 Unicast Test Scheduling ...................................... 242

8.2.4.2 Multicast Test Scheduling ................................... 244

8.3 Testing Cores ..................................................................................... 245

8.3.1 Core Wrapper Design.......................................................... 246

8.3.2 ILP Formulation ................................................................... 250

8.3.3 Heuristic Algorithms .......................................................... 253

8.3.4 PSO-Based Strategy ............................................................. 258

8.3.4.1 Particle Structure and Fitness ............................ 258

8.3.4.2 Evolution of Generations..................................... 259

8.4 Summary............................................................................................ 260

References ..................................................................................................... 260

9. Application-Specific Network-on-Chip Synthesis .............................. 263

9.1 Introduction ....................................................................................... 263

9.2 ASNoC Synthesis Problem .............................................................. 264

9.3 Literature Survey .............................................................................. 265

9.4 System-Level Floorplanning ........................................................... 268

9.4.1 Variables ................................................................................ 268

9.4.1.1 Independent Variables......................................... 268

9.4.1.2 Dependent Variables............................................ 268

9.4.2 Objective Function............................................................... 269

9.4.3 Constraints............................................................................ 269

9.4.4 Constraints for Mesh Topology ......................................... 270

9.5 Custom Interconnection Topology and Route Generation ......... 271

9.5.1 Variables ................................................................................ 272

9.5.1.1 Independent Variables......................................... 272

9.5.1.2 Derived Variables ................................................. 273

9.5.2 Objective Function............................................................... 273

9.5.3 Constraints............................................................................ 274

9.6 ASNoC Synthesis with Flexible Router Placement ...................... 277

9.6.1 ILP for Flexible Router Placement ..................................... 278

9.6.1.1 Variables ................................................................ 278

9.6.1.2 Objective Function ............................................... 279

9.6.1.3 Constraints ............................................................ 279

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Contents