514
References
7. L.W. Nagel, “SPICE2—A computer program to simulate semiconductor circuits,” Memo ERL-M250, Electronic Research Laboratory, University of California,
Berkeley, CA, May 1975.
8. J.M. Early, “Effects of space charge layer widening in junction transistors,”
Proceedings of the IRE, vol. 40, no. 11, pp. 1401–1406, 1952.
9. C.T. Kirk, Jr., “A theory of transistor cutoff frequency (fT) fall-off at high current
densities,” IRE Transactions on Electron Devices, vol. 9, no. 2, pp. 164–174, 1962.
10. C.T. Sah, R.N. Noyce, and W. Shockley, “Carrier generation and recombination
P-N junctions and P-N junction characteristics,” Proceedings of the IRE, vol. 45,
no. 9, pp. 1228–1243, 1957.
11. Si2. n.d. “Si2 (CMC) homepage.” https://www.si2.org/cmc_index.php, access
date: May 26, 2015.
12. C.C. McAndrew, J.A. Seitchik, D.F. Bowers, M. Dunn, M. Foisy, I. Getreu,
M. McSwain, S. Moinian, J. Parker, D.J. Roulston, M. Schroter, P. van Wijnen, and
L.F. Wagner, “VBIC95, the vertical bipolar inter-company model,” IEEE Journal of
Solid-State Circuits, vol. 31, no 10, pp. 1476–1483, 1996.
13. R. van der Toorn, T.C.J. Paasschens, and W.J. Kloosterman, “The Mextram
bipolar transistor model level 504.11.0,” NXP Semiconductors 2006 and Delft
University of Technology, the Netherlands, 2012.
14. M. Schroter and A. Chakravorty, Compact Hierarchical Bipolar Transistor Modeling
with HiCUM, World Scientific, Singapore, 2010.
Chapter 12
1. Synopsys Inc., HSPICE User Guide: Simulation and Analysis, B-2008.09,
Synopsys Inc., September 2008.
2. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W.
Liu, K. cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, and C. Hu, “BSIM4v4.8.0
MOSFET Model User’s Manual,” University of California, Berkeley, CA, 2013.
3. BSIMProPlus Basic Operations Guide, Product Version 2009.4, December 2009,
ProPlus Design Solutions, Inc.,
4. Agilent 85190A IC-CAP User’s Guide, 2008, Agilent Technologies. http://
cp.literature.agilent.com/litweb/pdf/iccap2008/pdf/icug.pdf.
5. S.K. Saha, “Managing technology CAD for competitive advantage: An efficient
approach for integrated circuit fabrication technology development,” IEEE
Transactions on Engineering Management, vol. 46, no. 2, pp. 221–229, 1999.
6. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
7. S.K. Saha, “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 104–115, 2014.
8. S.K. Saha, “Process variability modeling for VLSI circuit simulation,” in
Proceedings of the WCM, vol. 2, pp. 751–755, 2011.
9. S.K. Saha, “General methodology to develop statistical compact MOS models
for VLSI circuit simulation,” http://www.mos-ak.org/india/presentations/
Saha_MOS-AK_India12.pdf, accessed March 16, 2012.
References
7. L.W. Nagel, “SPICE2—A computer program to simulate semiconductor circuits,” Memo ERL-M250, Electronic Research Laboratory, University of California,
Berkeley, CA, May 1975.
8. J.M. Early, “Effects of space charge layer widening in junction transistors,”
Proceedings of the IRE, vol. 40, no. 11, pp. 1401–1406, 1952.
9. C.T. Kirk, Jr., “A theory of transistor cutoff frequency (fT) fall-off at high current
densities,” IRE Transactions on Electron Devices, vol. 9, no. 2, pp. 164–174, 1962.
10. C.T. Sah, R.N. Noyce, and W. Shockley, “Carrier generation and recombination
P-N junctions and P-N junction characteristics,” Proceedings of the IRE, vol. 45,
no. 9, pp. 1228–1243, 1957.
11. Si2. n.d. “Si2 (CMC) homepage.” https://www.si2.org/cmc_index.php, access
date: May 26, 2015.
12. C.C. McAndrew, J.A. Seitchik, D.F. Bowers, M. Dunn, M. Foisy, I. Getreu,
M. McSwain, S. Moinian, J. Parker, D.J. Roulston, M. Schroter, P. van Wijnen, and
L.F. Wagner, “VBIC95, the vertical bipolar inter-company model,” IEEE Journal of
Solid-State Circuits, vol. 31, no 10, pp. 1476–1483, 1996.
13. R. van der Toorn, T.C.J. Paasschens, and W.J. Kloosterman, “The Mextram
bipolar transistor model level 504.11.0,” NXP Semiconductors 2006 and Delft
University of Technology, the Netherlands, 2012.
14. M. Schroter and A. Chakravorty, Compact Hierarchical Bipolar Transistor Modeling
with HiCUM, World Scientific, Singapore, 2010.
Chapter 12
1. Synopsys Inc., HSPICE User Guide: Simulation and Analysis, B-2008.09,
Synopsys Inc., September 2008.
2. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W.
Liu, K. cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, and C. Hu, “BSIM4v4.8.0
MOSFET Model User’s Manual,” University of California, Berkeley, CA, 2013.
3. BSIMProPlus Basic Operations Guide, Product Version 2009.4, December 2009,
ProPlus Design Solutions, Inc.,
4. Agilent 85190A IC-CAP User’s Guide, 2008, Agilent Technologies. http://
cp.literature.agilent.com/litweb/pdf/iccap2008/pdf/icug.pdf.
5. S.K. Saha, “Managing technology CAD for competitive advantage: An efficient
approach for integrated circuit fabrication technology development,” IEEE
Transactions on Engineering Management, vol. 46, no. 2, pp. 221–229, 1999.
6. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
7. S.K. Saha, “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 104–115, 2014.
8. S.K. Saha, “Process variability modeling for VLSI circuit simulation,” in
Proceedings of the WCM, vol. 2, pp. 751–755, 2011.
9. S.K. Saha, “General methodology to develop statistical compact MOS models
for VLSI circuit simulation,” http://www.mos-ak.org/india/presentations/
Saha_MOS-AK_India12.pdf, accessed March 16, 2012.