513
References
103. L. Zhang, J. He, and M. Chan, “A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 143–146, 2012.
104. A. Pan and C.O. Chui, “A quasi-analytical model for double-gate tunneling fieldeffect transistors,” IEEE Electron Device Letters, vol. 33, no. 10, pp. 1468–1470, 2012.
105. L. Zhang, X. Lin, J. He, and M. Chan, “An analytical charge model for doublegate tunneling FETs,” IEEE Transactions on Electron Devices, vol. 59, no. 12, pp.
3217–3223, 2012.
106. B. Bhushan, K. Nayak, and V.R. Rao, “DC compact model for SOI tunnel
field-effect transistors,” IEEE Transactions on Electron Devices, vol. 59, no. 10,
pp. 2635–2642, 2012.
107. L. Zhang and M. Chan, “SPICE modeling of double-gate tunnel-FETs including channel transports,” IEEE Transactions on Electron Devices, vol. 61, no. 2,
pp. 300–307, 2014.
108. E. Arnold, “Charge-sheet model for silicon carbide inversion layers,” IEEE
Transactions on Electron Devices, vol. 46, no. 3, pp. 497–503, 1999.
109. X. Aymerich-Humet, F. Serra-Mestres, and J. Millan, “A generalized approximation of the Fermi–Dirac integrals,” Journal of Applied Physics, vol. 54, no. 5,
pp. 2850–2851, 1983.
110. Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain current model
for DG MOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107–109, 2004.
111. P.M. Solomon, J. Jopling, D.J. Frank, C.D’Emic, O. Dokumaci, P. Ronsheim, W.
Haensch, “Universal tunneling behavior in technologically relevant P/N junction diodes,” Journal of Applied Physics, vol. 95, no. 10, pp. 5800–5812, 2004.
112. E.O. Kane, “Theory of tunneling,” Journal of Applied Physics, vol. 32, no. 1,
pp. 83–91, 1961.
113. Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, and Y. Wang, “A novel
Si tunnel FET with 36 mV/dec subthreshold slope based on junction depletedmodulation through striped gate configuration,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 187–190, 2012.
114. H. Riel, K.E. Moselund, C. Bessire, M.T. Bjork, A. Schenk, H. Ghoneim, and
H. Schmid, “InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs,”
in IEEE International Electron Devices Meeting Technical Digest, pp. 391–394, 2012.
Chapter 11
1. D.J. Roulston, Bipolar Semiconductor Devices, McGraw-Hill, New York, 1990.
2. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge
University Press, Cambridge, 1998.
3. J. Bardeen and W.H. Brattain, “The transistor, a semiconductor triode,” Physical
Review, vol. 74, no. 2, pp. 230–231, 1948.
4. J.J. Ebers and J.L. Moll, “Large-signal behavior of junction transistors,”
Proceedings of the IRE, vol. 42, no. 12, pp. 1761–1772, 1954.
5. I. Getreu, Modeling the Bipolar Transistor, Tektronix, Beaverton, OR, 1976.
6. H.K. Gummel and C.C Poon, “An integral charge control model for bipolar
transistors,” Bell System Technical Journal, vol. 49, no. 5, pp. 827–852, 1970.
References
103. L. Zhang, J. He, and M. Chan, “A compact model for double-gate tunneling field-effect-transistors and its implications on circuit behaviors,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 143–146, 2012.
104. A. Pan and C.O. Chui, “A quasi-analytical model for double-gate tunneling fieldeffect transistors,” IEEE Electron Device Letters, vol. 33, no. 10, pp. 1468–1470, 2012.
105. L. Zhang, X. Lin, J. He, and M. Chan, “An analytical charge model for doublegate tunneling FETs,” IEEE Transactions on Electron Devices, vol. 59, no. 12, pp.
3217–3223, 2012.
106. B. Bhushan, K. Nayak, and V.R. Rao, “DC compact model for SOI tunnel
field-effect transistors,” IEEE Transactions on Electron Devices, vol. 59, no. 10,
pp. 2635–2642, 2012.
107. L. Zhang and M. Chan, “SPICE modeling of double-gate tunnel-FETs including channel transports,” IEEE Transactions on Electron Devices, vol. 61, no. 2,
pp. 300–307, 2014.
108. E. Arnold, “Charge-sheet model for silicon carbide inversion layers,” IEEE
Transactions on Electron Devices, vol. 46, no. 3, pp. 497–503, 1999.
109. X. Aymerich-Humet, F. Serra-Mestres, and J. Millan, “A generalized approximation of the Fermi–Dirac integrals,” Journal of Applied Physics, vol. 54, no. 5,
pp. 2850–2851, 1983.
110. Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain current model
for DG MOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107–109, 2004.
111. P.M. Solomon, J. Jopling, D.J. Frank, C.D’Emic, O. Dokumaci, P. Ronsheim, W.
Haensch, “Universal tunneling behavior in technologically relevant P/N junction diodes,” Journal of Applied Physics, vol. 95, no. 10, pp. 5800–5812, 2004.
112. E.O. Kane, “Theory of tunneling,” Journal of Applied Physics, vol. 32, no. 1,
pp. 83–91, 1961.
113. Q. Huang, R. Huang, Z. Zhan, Y. Qiu, W. Jiang, C. Wu, and Y. Wang, “A novel
Si tunnel FET with 36 mV/dec subthreshold slope based on junction depletedmodulation through striped gate configuration,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 187–190, 2012.
114. H. Riel, K.E. Moselund, C. Bessire, M.T. Bjork, A. Schenk, H. Ghoneim, and
H. Schmid, “InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs,”
in IEEE International Electron Devices Meeting Technical Digest, pp. 391–394, 2012.
Chapter 11
1. D.J. Roulston, Bipolar Semiconductor Devices, McGraw-Hill, New York, 1990.
2. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge
University Press, Cambridge, 1998.
3. J. Bardeen and W.H. Brattain, “The transistor, a semiconductor triode,” Physical
Review, vol. 74, no. 2, pp. 230–231, 1948.
4. J.J. Ebers and J.L. Moll, “Large-signal behavior of junction transistors,”
Proceedings of the IRE, vol. 42, no. 12, pp. 1761–1772, 1954.
5. I. Getreu, Modeling the Bipolar Transistor, Tektronix, Beaverton, OR, 1976.
6. H.K. Gummel and C.C Poon, “An integral charge control model for bipolar
transistors,” Bell System Technical Journal, vol. 49, no. 5, pp. 827–852, 1970.