512
References
88. C.D. Bessire, M.T. Björk, H. Schmid, A. Schenk, K.B. Reuter, and H. Riel, “Trapassisted tunneling in Si–InAs nanowire heterojunction tunnel diodes,” Nano
Letters, vol. 11, no. 10, pp. 4195–4199, 2011.
89. Y. Lu, “Geometry dependent tunnel FET performance—Dilemma of electrostatics vs. quantum confinement.” in Device Research Conference, pp. 17–18, 2010.
90. H. Schmid, K.E. Moselund, M.T. Björk, M. Richter, H. Ghoneim, C.D. Bessire,
and H. Riel, “Fabrication of vertical InAs–Si heterojunction tunnel field effect
transistors,” in Device Research Conference, pp. 181–182, 2011.
91. S. Poli, S. Reggiani, A. Gnudi, E. Gnani, and G. Baccarani, “Computational study
of the ultimate scaling limits of CNT tunneling devices,” IEEE Transactions on
Electron Devices, vol. 55, no. 1, 313–321, 2008.
92. S.O. Koswatta, M.S. Lundstrom, and D.E. Nikonov, “Band-to-band tunneling
in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling,” Nano Letters, vol. 7, no. 5, pp. 1160–1164,
2007.
93. J. Appenzeller, Y.-M. Lin, J. Knoch, Z. Chen, and P. Avouris, “Comparing carbon nanotube transistors—The ideal choice: a novel tunneling device design,”
IEEE Transactions on Electron Devices, vol. 52, no. 12, pp. 2568–2576, 2005.
94. M. Luisier and G. Klimeck, “Performance limitations of graphene nano ribbon
tunneling FETS due to line edge roughness,” in Device Research Conference,
pp. 201–202, 2009.
95. G. Fiori and G. Iannaccone, “Ultralow-voltage bilayer graphene tunnel FET,”
IEEE Electron Device Letters, vol. 30, no. 10, pp. 1096–1098, 2009.
96. D. Kim, Y. Lee, J. Cai, I. Lauer, L. Chang, S.J. Koster, D. Sylvester, D. Blaauw,
“Low power circuit design based on heterojunction tunneling transistors
(HETTs),” in Proceedings of the 2009 ACM/IEEE International Symposium on Low
power Electronics and Design, pp. 219–224, 2009.
97. V. Saripalli, G. Sun, A. Mishra, Y. Xie, S. Datta, and V. Narayanan, “Exploiting
heterogeneity for energy efficiency in chip multiprocessor,” IEEE Transactions
on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 2, pp. 109–119,
2011.
98. Y. Hong, Y. Yang, L. Yang, G. Samudra, C.H. Heng, and Y.C. Yeo, “SPICE behavioral model of the tunneling field-effect transistor for circuit simulation,” IEEE
Transactions on Circuits and Systems–II: Express Briefs, vol. 56, no. 12, pp. 946–950,
2009.
99. M.S. Kim, H. Liu, X. Li, S. Datta, and V. Narayanan, “Design and implementation
of low power mixed signal using a steep slope tunnel FET based SAR analogto-digital converters,” IEEE Transactions on Electron Devices, vol. 61, no. 11, pp.
3661–3667, 2014.
100. A.S. Verhulst, B. Soree, D. Leonelli, W.G. Vandenberghe, and G. Groeseneken,
“Modeling the single-gate, double-gate, and gate-all-around tunnel field-effecttransistor,” Journal of Applied Physics, vol. 107, no. 2, pp. 024518-1–024518-8,
2010.
101. M.G. Bardon, H.P. Neves, R. Puers, and C.V. Hoof, “Pseudo two-dimensional
model for double-gate tunnel FETs considering the junctions depletion regions,”
IEEE Transactions on Electron Devices, vol. 57, no. 4, pp. 827–834, 2010.
102. P. Solomon, D.J. Franke, and S.O. Koswatta, “Compact model and performance
estimation for tunneling nanowire FET,” in 69th Annual Device Research Conference,
pp. 197–198, 2011.
References
88. C.D. Bessire, M.T. Björk, H. Schmid, A. Schenk, K.B. Reuter, and H. Riel, “Trapassisted tunneling in Si–InAs nanowire heterojunction tunnel diodes,” Nano
Letters, vol. 11, no. 10, pp. 4195–4199, 2011.
89. Y. Lu, “Geometry dependent tunnel FET performance—Dilemma of electrostatics vs. quantum confinement.” in Device Research Conference, pp. 17–18, 2010.
90. H. Schmid, K.E. Moselund, M.T. Björk, M. Richter, H. Ghoneim, C.D. Bessire,
and H. Riel, “Fabrication of vertical InAs–Si heterojunction tunnel field effect
transistors,” in Device Research Conference, pp. 181–182, 2011.
91. S. Poli, S. Reggiani, A. Gnudi, E. Gnani, and G. Baccarani, “Computational study
of the ultimate scaling limits of CNT tunneling devices,” IEEE Transactions on
Electron Devices, vol. 55, no. 1, 313–321, 2008.
92. S.O. Koswatta, M.S. Lundstrom, and D.E. Nikonov, “Band-to-band tunneling
in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling,” Nano Letters, vol. 7, no. 5, pp. 1160–1164,
2007.
93. J. Appenzeller, Y.-M. Lin, J. Knoch, Z. Chen, and P. Avouris, “Comparing carbon nanotube transistors—The ideal choice: a novel tunneling device design,”
IEEE Transactions on Electron Devices, vol. 52, no. 12, pp. 2568–2576, 2005.
94. M. Luisier and G. Klimeck, “Performance limitations of graphene nano ribbon
tunneling FETS due to line edge roughness,” in Device Research Conference,
pp. 201–202, 2009.
95. G. Fiori and G. Iannaccone, “Ultralow-voltage bilayer graphene tunnel FET,”
IEEE Electron Device Letters, vol. 30, no. 10, pp. 1096–1098, 2009.
96. D. Kim, Y. Lee, J. Cai, I. Lauer, L. Chang, S.J. Koster, D. Sylvester, D. Blaauw,
“Low power circuit design based on heterojunction tunneling transistors
(HETTs),” in Proceedings of the 2009 ACM/IEEE International Symposium on Low
power Electronics and Design, pp. 219–224, 2009.
97. V. Saripalli, G. Sun, A. Mishra, Y. Xie, S. Datta, and V. Narayanan, “Exploiting
heterogeneity for energy efficiency in chip multiprocessor,” IEEE Transactions
on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 2, pp. 109–119,
2011.
98. Y. Hong, Y. Yang, L. Yang, G. Samudra, C.H. Heng, and Y.C. Yeo, “SPICE behavioral model of the tunneling field-effect transistor for circuit simulation,” IEEE
Transactions on Circuits and Systems–II: Express Briefs, vol. 56, no. 12, pp. 946–950,
2009.
99. M.S. Kim, H. Liu, X. Li, S. Datta, and V. Narayanan, “Design and implementation
of low power mixed signal using a steep slope tunnel FET based SAR analogto-digital converters,” IEEE Transactions on Electron Devices, vol. 61, no. 11, pp.
3661–3667, 2014.
100. A.S. Verhulst, B. Soree, D. Leonelli, W.G. Vandenberghe, and G. Groeseneken,
“Modeling the single-gate, double-gate, and gate-all-around tunnel field-effecttransistor,” Journal of Applied Physics, vol. 107, no. 2, pp. 024518-1–024518-8,
2010.
101. M.G. Bardon, H.P. Neves, R. Puers, and C.V. Hoof, “Pseudo two-dimensional
model for double-gate tunnel FETs considering the junctions depletion regions,”
IEEE Transactions on Electron Devices, vol. 57, no. 4, pp. 827–834, 2010.
102. P. Solomon, D.J. Franke, and S.O. Koswatta, “Compact model and performance
estimation for tunneling nanowire FET,” in 69th Annual Device Research Conference,
pp. 197–198, 2011.