511
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Narayanan, D. Schlom, A. Liu, and S. Datta, “Experimental demonstration
of 100 nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field
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IEEE International Electron Devices Meeting Technical Digest, pp. 137.1–137.4,
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Electron Devices, vol. 58, no. 9, pp. 2990–2995, 2011.
82. S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, and S. Datta, “Temperaturedependent characteristics of a vertical tunnel FET,” IEEE Electron Device Letters,
vol. 31, no. 6, pp. 564–566, 2010.
83. L. Wang, E. Yu, Y. Taur Y and P. Asbeck, “Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications,”
IEEE Electron Device Letters, vol. 31, no. 5, pp. 431–433, 2010.
84. D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu,
D. Loubychev, J. Fastenau, and S. Datta, “Experimental staggered-source and
N+pocket-doped channel III–V tunnel field-effect transistors and their scalabilities,” Applied Physics Express, vol. 4, no. 2, pp. 024105-1–024105-3, 2011.
85. G. Zhou, Y. Lu, R. Li, Q. Zhang, W. Huang, Q. Liu, T. Vasen, H. Zhu, J. Kuo,
S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. Xing, “Self-aligned
InAs/Al 0.45 Ga 0.55 Sb vertical tunnel FETs,” in Device Research Conference, pp. 205–206,
2011.
86. K. Tomioka, J. Motohisa, S. Hara and T. Fukui, “Control of InAs nanowire
growth directions on Si,” Nano Letters, vol. 8, no. 10, pp. 3475–3480, 2008.
87. M.T. Björk, H. Schmid, C.D. Bessire, K.E. Moselund, H. Ghoneim, S. Karg,
E. Lortscher, and H. Riel, “Si–InAs heterojunction Esaki tunnel diodes with high
current densities,” Applied Physics Letters, vol. 97, no. 16, pp. 163501-1–163501-3,
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References
74. K.E. Moselund, H. Ghoneim, M.T. Bjork, H. Schmid, S. Kang, E. Lortscher, W. Reis,
and H. Riel, “Comparison of VLS grown Si NW tunnel FETs with different
gate stacks,” in Proceedings of the European Solid-State Device Research Conference,
pp. 448–451, 2009.
75. O.M. Nayfeh, C.N. Chleirigh, J. Hennessy, L. Gomez, J.L. Hoyt, and D.A. Antonidis,
“Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions,” IEEE Electron Device Letters, vol. 29,
no. 9, pp. 1074–1077, 2008.
76. K. Boucart, A.M. Ionescu, and W. Riess, “Asymmetrically strained all-silicon
tunnel FETs featuring 1V operation,” in Proceedings of the European Solid-State
Device Research Conference, pp. 452–456, 2009.
77. K. Boucart, W. Riess, and A.M. Ionescu, “Lateral strain profile as key technology
booster for all-silicon tunnel FETs,” IEEE Electron Device Letters, vol. 30, no. 6,
pp. 656–658, 2009.
78. C. Le Royer and F. Mayer, “Exhaustive experimental study of tunnel field effect
transistors (TFETs): From materials to architecture,” in International Conference
on Ultimate Integration of Silicon, 53–56, 2009.
79. W.-Y. Loh, “Sub-60nm Si tunnel field effect transistors with I on > 100 μA/μm,”
in Proceedings of the European Solid-State Device Research Conference, pp. 162–165,
2010.
80. S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallet, A. Ali, T. Mayer, V.
Narayanan, D. Schlom, A. Liu, and S. Datta, “Experimental demonstration
of 100 nm channel length In 0.53 Ga 0.47 As-based vertical inter-band tunnel field
effect transistors (TFET) for ultra low-power logic and SRAM applications,”
IEEE International Electron Devices Meeting Technical Digest, pp. 137.1–137.4,
2009.
81. H. Zhao, Y. Chen, Y. Wang, F. Zhou, F. Xue, and J. Lee, “InGaAs tunneling fieldeffect transistors with atomic-layer-deposited gate oxides,” IEEE Transactions on
Electron Devices, vol. 58, no. 9, pp. 2990–2995, 2011.
82. S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, and S. Datta, “Temperaturedependent characteristics of a vertical tunnel FET,” IEEE Electron Device Letters,
vol. 31, no. 6, pp. 564–566, 2010.
83. L. Wang, E. Yu, Y. Taur Y and P. Asbeck, “Design of tunneling field-effect transistors based on staggered heterojunctions for ultralow-power applications,”
IEEE Electron Device Letters, vol. 31, no. 5, pp. 431–433, 2010.
84. D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu,
D. Loubychev, J. Fastenau, and S. Datta, “Experimental staggered-source and
N+pocket-doped channel III–V tunnel field-effect transistors and their scalabilities,” Applied Physics Express, vol. 4, no. 2, pp. 024105-1–024105-3, 2011.
85. G. Zhou, Y. Lu, R. Li, Q. Zhang, W. Huang, Q. Liu, T. Vasen, H. Zhu, J. Kuo,
S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. Xing, “Self-aligned
InAs/Al 0.45 Ga 0.55 Sb vertical tunnel FETs,” in Device Research Conference, pp. 205–206,
2011.
86. K. Tomioka, J. Motohisa, S. Hara and T. Fukui, “Control of InAs nanowire
growth directions on Si,” Nano Letters, vol. 8, no. 10, pp. 3475–3480, 2008.
87. M.T. Björk, H. Schmid, C.D. Bessire, K.E. Moselund, H. Ghoneim, S. Karg,
E. Lortscher, and H. Riel, “Si–InAs heterojunction Esaki tunnel diodes with high
current densities,” Applied Physics Letters, vol. 97, no. 16, pp. 163501-1–163501-3,
2010.