510
References
57. K. Boucart and A.M. Ionescu, “Double-gate tunnel FET with high-κ gate dielectric,” IEEE Transactions on Electron Devices, vol. 54, no. 7, 1725–1733, 2007.
58. K. Bhuwalka, J. Schulze, and I. Eisele, “A simulation approach to optimize the
electrical parameters of a vertical tunnel FET,” IEEE Transactions on Electron
Devices, vol. 52, no. 7, pp. 1541–1547, 2005.
59. A. Oritiz-Conde, F.J.G. Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, and Y. Yue,
“A review of recent MOSFET threshold voltage extraction methods,” Microelectronics Reliability, vol. 42, no. 4/5, pp. 583–596, 2002.
60. K. Boucart and A.M. Ionescu, “A new definition of threshold voltage in tunnel
FETs,” Solid-State Electronics, vol. 52, no. 9, pp. 1318–1323, 2008.
61. K. Boucart and A.M. Ionescu, “Length scaling of the double gate tunnel
FET with a high-κ gate dielectric,” Solid-State Electronics, vol. 51, no. 11/12,
pp. 1500–1507, 2007.
62. C. Sandow, J. Knoch, C. Urban, Q.-T. Zhao, and S. Mantl, “Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect
transistors,” Solid-State Electronics, vol. 53, no. 10, 1126–1129, 2009.
63. A.M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient
electronic switches,” Nature, vol. 479, pp. 329–337, 2011.
64. J. Appenzeller, J. Knoch, M.T. Björk, H. Riel, and W. Riess, “Toward nanowire
electronics,” IEEE Transactions on Electron Devices, vol. 55, no. 11, 2827–2845, 2008.
65. A.M. Ionescu, K. Boucart, K.E. Moselund, and V. Pott, Small Swing Switches,
Cambridge University Press, Cambridge, 2011.
66. D. Leonelli, A. Vandooren, R. Rooyackers, S. De Gendt, M.M. Heyns, and
G. Groeseneken, “Optimization of tunnel FETs: impact of gate oxide thickness,
implantation and annealing conditions,” in Proceedings of the European Solid-State
Device Research Conference, pp. 170–173, 2010.
67. C. Hu, P. Patel, A. Bowonder, J. Kanghoon, S.-H. Kim, W.Y. Loh, C.Y. Kang, J. Oh,
P. Majhi, A. Javey, T.-J.K. Liu, and R. Jammy, “Prospect of tunneling green transistor for 0.1 V CMOS,” in IEEE International Electron Devices Meeting Technical
Digest, pp. 387–390, 2010.
68. R. Asra, M. Shrivastava, K.V.R.M. Murali, R.K. Pandey, H. Gossner, and V.R.
Rao, “A tunnel FET for V DD scaling below 0.6V with a CMOS-comparable performance,” IEEE Transactions on Electron Devices, vol. 58, no. 7, pp. 1855–1863, 2011.
69. L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, and A.M. Ionescu, “TunnelFET architecture with improved performance due to enhanced gate modulation of the tunneling barrier,” in Device Research Conference, pp. 111–112, 2011.
70. A.S. Verhulst, W.G. Vandenberghe, K. Maex, S. De Gendt, M.M. Heyns, and
G. Groeseneken, “Complementary silicon-based heterostructure tunnel-FETs
with high tunnel rates,” IEEE Electron Device Letters vol. 29, no. 12, pp. 1398–1401,
2008.
71. J. Knoch, “Optimizing tunnel FET performance–impact of device structure,
transistor dimensions and choice of material,” in Symposium on VLSI Technology,
pp. 45–46, 2009.
72. J. Knoch and J. Appenzeller, “Modeling of high-performance p-type III–V heterojunction tunnel FETs,” IEEE Electron Device Letters, vol. 31, no. 4, pp. 305–307, 2010.
73. S.O. Koswatta, S.J. Koester, and W. Haensch, “On the possibility of obtaining
MOSFET-like performance and sub-60-mV/dec swing in 1-D broken-gap tunnel
transistors,” IEEE Transactions on Electron Devices, vol. 57, no. 12, pp. 3222–3223,
2010.
References
57. K. Boucart and A.M. Ionescu, “Double-gate tunnel FET with high-κ gate dielectric,” IEEE Transactions on Electron Devices, vol. 54, no. 7, 1725–1733, 2007.
58. K. Bhuwalka, J. Schulze, and I. Eisele, “A simulation approach to optimize the
electrical parameters of a vertical tunnel FET,” IEEE Transactions on Electron
Devices, vol. 52, no. 7, pp. 1541–1547, 2005.
59. A. Oritiz-Conde, F.J.G. Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, and Y. Yue,
“A review of recent MOSFET threshold voltage extraction methods,” Microelectronics Reliability, vol. 42, no. 4/5, pp. 583–596, 2002.
60. K. Boucart and A.M. Ionescu, “A new definition of threshold voltage in tunnel
FETs,” Solid-State Electronics, vol. 52, no. 9, pp. 1318–1323, 2008.
61. K. Boucart and A.M. Ionescu, “Length scaling of the double gate tunnel
FET with a high-κ gate dielectric,” Solid-State Electronics, vol. 51, no. 11/12,
pp. 1500–1507, 2007.
62. C. Sandow, J. Knoch, C. Urban, Q.-T. Zhao, and S. Mantl, “Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect
transistors,” Solid-State Electronics, vol. 53, no. 10, 1126–1129, 2009.
63. A.M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient
electronic switches,” Nature, vol. 479, pp. 329–337, 2011.
64. J. Appenzeller, J. Knoch, M.T. Björk, H. Riel, and W. Riess, “Toward nanowire
electronics,” IEEE Transactions on Electron Devices, vol. 55, no. 11, 2827–2845, 2008.
65. A.M. Ionescu, K. Boucart, K.E. Moselund, and V. Pott, Small Swing Switches,
Cambridge University Press, Cambridge, 2011.
66. D. Leonelli, A. Vandooren, R. Rooyackers, S. De Gendt, M.M. Heyns, and
G. Groeseneken, “Optimization of tunnel FETs: impact of gate oxide thickness,
implantation and annealing conditions,” in Proceedings of the European Solid-State
Device Research Conference, pp. 170–173, 2010.
67. C. Hu, P. Patel, A. Bowonder, J. Kanghoon, S.-H. Kim, W.Y. Loh, C.Y. Kang, J. Oh,
P. Majhi, A. Javey, T.-J.K. Liu, and R. Jammy, “Prospect of tunneling green transistor for 0.1 V CMOS,” in IEEE International Electron Devices Meeting Technical
Digest, pp. 387–390, 2010.
68. R. Asra, M. Shrivastava, K.V.R.M. Murali, R.K. Pandey, H. Gossner, and V.R.
Rao, “A tunnel FET for V DD scaling below 0.6V with a CMOS-comparable performance,” IEEE Transactions on Electron Devices, vol. 58, no. 7, pp. 1855–1863, 2011.
69. L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, and A.M. Ionescu, “TunnelFET architecture with improved performance due to enhanced gate modulation of the tunneling barrier,” in Device Research Conference, pp. 111–112, 2011.
70. A.S. Verhulst, W.G. Vandenberghe, K. Maex, S. De Gendt, M.M. Heyns, and
G. Groeseneken, “Complementary silicon-based heterostructure tunnel-FETs
with high tunnel rates,” IEEE Electron Device Letters vol. 29, no. 12, pp. 1398–1401,
2008.
71. J. Knoch, “Optimizing tunnel FET performance–impact of device structure,
transistor dimensions and choice of material,” in Symposium on VLSI Technology,
pp. 45–46, 2009.
72. J. Knoch and J. Appenzeller, “Modeling of high-performance p-type III–V heterojunction tunnel FETs,” IEEE Electron Device Letters, vol. 31, no. 4, pp. 305–307, 2010.
73. S.O. Koswatta, S.J. Koester, and W. Haensch, “On the possibility of obtaining
MOSFET-like performance and sub-60-mV/dec swing in 1-D broken-gap tunnel
transistors,” IEEE Transactions on Electron Devices, vol. 57, no. 12, pp. 3222–3223,
2010.