509
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C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J.K. Liu, and C. Hu, “Si tunnel
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44. T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-gate
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Devices Meeting Technical Digest, pp. 947–949, 2008.
45. S.H. Kim, H. Kam, C. Hu, and T.-J.K. Liu, “Germanium-source tunnel field
effect transistors with record high ION/IOFF,” in Symposium on VLSI Technology,
pp. 178–179, 2009.
46. Y. Khatami and K. Banerjee, “Steep subthreshold slope n- and p-type tunnel-FET
devices for low-power and energy-efficient digital circuits,” IEEE Transactions on
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47. L.D. Landau and E.M. Lifshitz, Quantum Mechanics, Addison-Wesley, Reading,
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50. M. Luisier and G. Klimeck, “Simulation of nanowire tunneling transistors: From
the Wentzel- Kramers–Brillouin approximation to full-band phonon-assisted
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2010.
51. J. Knoch and J. Appenzeller, “A novel concept for field-effect transistors—The
tunneling carbon nanotube FET,” in Device Research Conference, 153–156, 2005.
52. B. Streetman and S. Banerjee, Solid State Electronic Devices, 7th edition, PrenticeHall, Englewood Cliffs, NJ, 2014.
53. J.-P. Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics, vol. 48, no. 6,
pp. 897–905, 2004.
54. K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele,
“P-channel tunnel field-effect transistors down to sub-50 nm channel lengths,”
Japan Journal of Applied Physics, vol. 45, no. 4B, pp. 3106–3109, 2006.
55. E.-H. Toh, G.H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C.
Yeo, “Device design and scalability of a double-gate tunneling field-effect transistor with silicon-germanium source,” Japan Journal of Applied Physics, vol. 47,
no. 4, pp. 2593–2597, 2008.
56. K.K. Bhuwalka, J. Schulze, and I. Eisele, “Scaling the vertical tunnel FET
with tunnel bandgap modulation and gate workfunction engineering,” IEEE
Transactions on Electron Devices, vol. 52, no. 5, pp. 909–917, 2005.
References
41. F. Mayer, C.L. Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone,
B. Previtali, and S. Deleonibus, “Impact of SOI, Si 1-x Ge x OI and GeOI substrates on
CMOS compatible tunnel FET performance,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 163–166, 2008.
42. K. Jeon, W.-Y. Loh, P. Patel, C.Y. Kang, J. Oh, A. Bowonder, C. Park, C.S. Park,
C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J.K. Liu, and C. Hu, “Si tunnel
transistors with a novel silicided source and 46 mV/dec swing,” in Symposium
on VLSI Technology, pp. 121–122, 2010,
43. D. Leonelli, A. Vandooren, R. Rooyackers, A.S. Verhulst, S.D. Gendt, M.M.
Heyns, and G. Groeseneken, “Performance enhancement in multi gate tunneling field effect transistors by scaling the fin-width,” Japan Journal of Applied
Physics, vol. 49, no. 4, 04DC10, 2010.
44. T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-gate
strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 947–949, 2008.
45. S.H. Kim, H. Kam, C. Hu, and T.-J.K. Liu, “Germanium-source tunnel field
effect transistors with record high ION/IOFF,” in Symposium on VLSI Technology,
pp. 178–179, 2009.
46. Y. Khatami and K. Banerjee, “Steep subthreshold slope n- and p-type tunnel-FET
devices for low-power and energy-efficient digital circuits,” IEEE Transactions on
Electron Devices, vol. 56, no. 11, pp. 2752–2761, 2009.
47. L.D. Landau and E.M. Lifshitz, Quantum Mechanics, Addison-Wesley, Reading,
MA, 1990.
48. S.M. Sze, Physics of Semiconductor Devices, 3rd edition, John Wiley, New York,
1998.
49. J. Knoch, D. Mantl, and J. Appenzeller, “Impact of the dimensionality on the
performance of tunneling FETs: Bulk versus one-dimensional devices,” SolidState Electronics, vol. 51, no. 4, pp. 572–578, 2007.
50. M. Luisier and G. Klimeck, “Simulation of nanowire tunneling transistors: From
the Wentzel- Kramers–Brillouin approximation to full-band phonon-assisted
tunneling” Journal of Applied Physics, vol. 107, no. 8, pp. 084507-1–084507-6,
2010.
51. J. Knoch and J. Appenzeller, “A novel concept for field-effect transistors—The
tunneling carbon nanotube FET,” in Device Research Conference, 153–156, 2005.
52. B. Streetman and S. Banerjee, Solid State Electronic Devices, 7th edition, PrenticeHall, Englewood Cliffs, NJ, 2014.
53. J.-P. Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics, vol. 48, no. 6,
pp. 897–905, 2004.
54. K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele,
“P-channel tunnel field-effect transistors down to sub-50 nm channel lengths,”
Japan Journal of Applied Physics, vol. 45, no. 4B, pp. 3106–3109, 2006.
55. E.-H. Toh, G.H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C.
Yeo, “Device design and scalability of a double-gate tunneling field-effect transistor with silicon-germanium source,” Japan Journal of Applied Physics, vol. 47,
no. 4, pp. 2593–2597, 2008.
56. K.K. Bhuwalka, J. Schulze, and I. Eisele, “Scaling the vertical tunnel FET
with tunnel bandgap modulation and gate workfunction engineering,” IEEE
Transactions on Electron Devices, vol. 52, no. 5, pp. 909–917, 2005.