508
References
24. T. Baba, “Proposal for surface tunnel transistors,” Japan Journal of Applied
Physics, vol. 31, no. 4B, pp. L455–L457, 1992.
25. T. Uemura and T. Baba, “First observation of negative differential resistance in
surface tunnel transistors,” Japan Journal of Applied Physics, vol. 33, no. 2B,
pp. L207–L210, 1994.
26. H. Kawaura, N. Iguchi, and T. Baba, “Fabrication of silicon surface tunnel
transistors - Extended Abstract,” in 2nd International Workshop on Quantum
Functional Devices, p. 62, May 1995.
27. Y. Omura, “Negative conductance properties in extremely thin silicon-on-insulator (SOI) insulated-gate pn-junction devices (SOI surface tunnel transistors),”
Japan Journal of Applied Physics, vol. 35, no. 11A, pp. L1401–L1403, 1996.
28. J. Koga and A. Toriumi, “Negative differential conductance at room temperature in three-terminal silicon surface junction tunnel transistor,” Applied
Physics Letters, vol. 70, no. 16, pp. 2138–2140, 1997.
29. J. Koga and A. Toriumi, “Three-terminal silicon surface junction tunnel device
for room temperature operation,” IEEE Electron Device Letters, vol. 20, no. 10,
pp. 529–531, 1999.
30. T. Uemura and T. Baba, “First demonstration of a planar-type surface tunnel
transistor (STT): Lateral interband tunnel device,” Solid-State Electronics, vol. 40,
no. 1, pp. 519–522, 1996.
31. T. Uemura and T. Baba, “Large enhancement of interband tunneling current
densities of over 105 A/cm2 in In0:53Ga0:47As-based surface tunnel transistors,” IEEE Electron Device Letters, vol. 18, no. 5, pp. 225–227, 1997.
32. Y.J. Chun, T. Uemura, and T. Baba, “Self-aligned surface tunnel transistors fabricated by a regrowth technique,” Japan Journal of Applied Physics, vol. 38, no. 10B,
pt. 2, pp. L1163–L1165, 1999.
33. Y.J. Chun, T. Uemura, and T. Baba, “Fabrication of self-aligned surface tunnel
transistors with a 80-nm gate length,” Japan Journal of Applied Physics, vol. 39,
no. 12B, pt. 2, pp. L1273–L1276, 2000.
34. W.M. Reddick and G.A.J. Amartunga, “Silicon surface tunnel transistor,”
Applied Physics Letters, vol. 67, no. 4, pp. 494–496, 1995.
35. W. Hansch, C. Fink, J. Schulze, and I. Eisele, “A vertical MOS-gated Esaki
tunneling transistor in silicon,” Thin Solid Films, vol. 369, vol. 1/2, pp. 387–389,
2000.
36. C. Aydin, A. Zaslevsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and
S. Deleonibus, “Lateral interband tunneling transistor in silicon-on- insulator,”
Applied Physics Letters, vol. 84, no. 10, pp. 1780–1782, 2004.
37. Q. Zhang, W. Zhao, and A. Seabaugh, “Analytic expression and approach for low
subthreshold-swing tunnel transistors,” in Device Research Conference, pp. 161–162,
2005.
38. Q. Zhang, W. Zhao, and A. Seabaugh, “Low-subthreshold-swing tunnel transistors,” IEEE Electron Device Letters, vol. 27, no. 4, 297–300, 2006.
39. Y. Lu, S. Bangsaruntip, X. Wang, L. Zhang, Y. Nishi, and H. Dai, “DNA functionalization of carbon nanotubes for ultrathin atomic layer deposition of high-k
dielectrics for nanotube transistors with 60 mV/decade switching,” Journal of
American Chemical Soceity, vol. 128, no. 11, pp. 3518–3519, 2006.
40. W.Y. Choi, B.-G. Park, J.D. Lee, and T.-J.K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron
Device Letters, vol. 28, no. 8, pp. 743–745, 2007.
References
24. T. Baba, “Proposal for surface tunnel transistors,” Japan Journal of Applied
Physics, vol. 31, no. 4B, pp. L455–L457, 1992.
25. T. Uemura and T. Baba, “First observation of negative differential resistance in
surface tunnel transistors,” Japan Journal of Applied Physics, vol. 33, no. 2B,
pp. L207–L210, 1994.
26. H. Kawaura, N. Iguchi, and T. Baba, “Fabrication of silicon surface tunnel
transistors - Extended Abstract,” in 2nd International Workshop on Quantum
Functional Devices, p. 62, May 1995.
27. Y. Omura, “Negative conductance properties in extremely thin silicon-on-insulator (SOI) insulated-gate pn-junction devices (SOI surface tunnel transistors),”
Japan Journal of Applied Physics, vol. 35, no. 11A, pp. L1401–L1403, 1996.
28. J. Koga and A. Toriumi, “Negative differential conductance at room temperature in three-terminal silicon surface junction tunnel transistor,” Applied
Physics Letters, vol. 70, no. 16, pp. 2138–2140, 1997.
29. J. Koga and A. Toriumi, “Three-terminal silicon surface junction tunnel device
for room temperature operation,” IEEE Electron Device Letters, vol. 20, no. 10,
pp. 529–531, 1999.
30. T. Uemura and T. Baba, “First demonstration of a planar-type surface tunnel
transistor (STT): Lateral interband tunnel device,” Solid-State Electronics, vol. 40,
no. 1, pp. 519–522, 1996.
31. T. Uemura and T. Baba, “Large enhancement of interband tunneling current
densities of over 105 A/cm2 in In0:53Ga0:47As-based surface tunnel transistors,” IEEE Electron Device Letters, vol. 18, no. 5, pp. 225–227, 1997.
32. Y.J. Chun, T. Uemura, and T. Baba, “Self-aligned surface tunnel transistors fabricated by a regrowth technique,” Japan Journal of Applied Physics, vol. 38, no. 10B,
pt. 2, pp. L1163–L1165, 1999.
33. Y.J. Chun, T. Uemura, and T. Baba, “Fabrication of self-aligned surface tunnel
transistors with a 80-nm gate length,” Japan Journal of Applied Physics, vol. 39,
no. 12B, pt. 2, pp. L1273–L1276, 2000.
34. W.M. Reddick and G.A.J. Amartunga, “Silicon surface tunnel transistor,”
Applied Physics Letters, vol. 67, no. 4, pp. 494–496, 1995.
35. W. Hansch, C. Fink, J. Schulze, and I. Eisele, “A vertical MOS-gated Esaki
tunneling transistor in silicon,” Thin Solid Films, vol. 369, vol. 1/2, pp. 387–389,
2000.
36. C. Aydin, A. Zaslevsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and
S. Deleonibus, “Lateral interband tunneling transistor in silicon-on- insulator,”
Applied Physics Letters, vol. 84, no. 10, pp. 1780–1782, 2004.
37. Q. Zhang, W. Zhao, and A. Seabaugh, “Analytic expression and approach for low
subthreshold-swing tunnel transistors,” in Device Research Conference, pp. 161–162,
2005.
38. Q. Zhang, W. Zhao, and A. Seabaugh, “Low-subthreshold-swing tunnel transistors,” IEEE Electron Device Letters, vol. 27, no. 4, 297–300, 2006.
39. Y. Lu, S. Bangsaruntip, X. Wang, L. Zhang, Y. Nishi, and H. Dai, “DNA functionalization of carbon nanotubes for ultrathin atomic layer deposition of high-k
dielectrics for nanotube transistors with 60 mV/decade switching,” Journal of
American Chemical Soceity, vol. 128, no. 11, pp. 3518–3519, 2006.
40. W.Y. Choi, B.-G. Park, J.D. Lee, and T.-J.K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron
Device Letters, vol. 28, no. 8, pp. 743–745, 2007.