507
References
7. K. Gopalakrishnan, P.B. Griffin, and J.D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” in IEEE International
Electron Devices Meeting Technical Digest, pp. 289–292, 2002.
8. W.Y. Choi, J.D. Lee, and B.-G. Park, “Integration process of impact ionization
metal-oxide-semiconductor devices with tunneling field-effect transistors and
metal-oxide-semiconductor field-effect transistors,” Japan Journal of Applied
Physics, vol. 46, no. 1R, pp. 122–124, 2007.
9. C.-W. Lee, A.N. Nazarov, I. Ferain, N.D. Akhavan, R.Yan, P. Razavi, R.Yu,
R.T. Doria, and J.-P. Colinge, “Low subthreshold slope in junctionless multigate transistors,” Applied Physics Letters, vol. 96, no.10, p. 102106, 2010.
10. E.-H. Toh, G.H. Wang, L. Chan, D. Weeks, M. Bauer, J. Spear, S.G. Thomas,
G. Samudra, and Y.-C. Yeo, “Co-integration of in situ doped silicon-carbide source
and silicon-carbon i-region in p-channel silicon nanowire impact-ionization
transistor,” IEEE Electron Device Letters, vol. 29, no. 7, pp. 731–733, 2008.
11. S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Letters, vol. 8, no. 2, pp. 405–410,
2008.
12. H. Nathanson, W. Newell, R. Wickstro, and J. Davis, “Resonant gate transistor,”
IEEE Transactions on Electron Devices, vol. ED-14, no. 3, pp. 117–133, 1967.
13. A.M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M.J. Declercq, P. Renaud, C. Hilbert,
P. Fluckiger, and G.A. Racine, “Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture,” in
Proceedings of the International Symposium on Quality Electronic Design, pp. 496–501,
2002.
14. H. Kam, D.T. Lee, R.T. Howe, and T.-J. King, “A new nano-electro-mechanical
field effect transistor (NEMFET) design for low-power electronics,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 463–466, 2005.
15. A.M. Ionescu, K. Boucart, K.E. Moselund, V. Pott, and D. Tsamados, “Small
slope micro/nano-electronic switches,” in Proceedings of the International
Semiconductor Conference, pp. 397–402, 2007.
16. A.C. Seabaugh and Q. Zhang, “Low voltage tunnel transistors for beyond
CMOS logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095–2110, 2010.
17. C. Zener, “A theory of the electrical breakdown of solid dielectrics,” Proceedings
of the Royal Society of London, vol. A145, no. 8555, pp. 523–529, 1934.
18. Y. Lu, A. Seabaugh, P. Fay, S.J. Koester, S.E. Laux, W. Haensch, and S.O. Koswatta,
“Geometry dependent tunnel FET performance-dilemma of electrostatics vs.
quantum confinement,” in Device Research Conference, pp. 17–18, 2010.
19. C. Hu, “Green transistor as a solution to the IC power crisis,” in 9th International
Conference on Solid-State and Integrated-Circuit Technology, pp. 16–20, 2008.
20. O.M. Stuetzer, “Junction fieldistors,” Proceedings of the IRE, vol. 40, no. 11,
pp. 1377–1381, 1952.
21. L. Esaki, “New phenomenon in narrow germanium p-n junctions,” Physical
Reviews, vol. 109, no. 2, pp. 603–604, 1958.
22. J. Quinn, G. Kawamoto, and B. McCombe, “Subband spectroscopy by surface
channel tunneling,” Surface Science, vol. 73, no. 1, pp. 190–196, 1978.
23. J.P. Leburton, J. Kolodzey, and S. Biggs, “Bipolar tunneling field-effect transistor: A three-terminal negative differential resistance device for high-speed
applications,” Applied Physics Letters, vol. 52, no. 9, pp. 1608–1620, 1988.
References
7. K. Gopalakrishnan, P.B. Griffin, and J.D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” in IEEE International
Electron Devices Meeting Technical Digest, pp. 289–292, 2002.
8. W.Y. Choi, J.D. Lee, and B.-G. Park, “Integration process of impact ionization
metal-oxide-semiconductor devices with tunneling field-effect transistors and
metal-oxide-semiconductor field-effect transistors,” Japan Journal of Applied
Physics, vol. 46, no. 1R, pp. 122–124, 2007.
9. C.-W. Lee, A.N. Nazarov, I. Ferain, N.D. Akhavan, R.Yan, P. Razavi, R.Yu,
R.T. Doria, and J.-P. Colinge, “Low subthreshold slope in junctionless multigate transistors,” Applied Physics Letters, vol. 96, no.10, p. 102106, 2010.
10. E.-H. Toh, G.H. Wang, L. Chan, D. Weeks, M. Bauer, J. Spear, S.G. Thomas,
G. Samudra, and Y.-C. Yeo, “Co-integration of in situ doped silicon-carbide source
and silicon-carbon i-region in p-channel silicon nanowire impact-ionization
transistor,” IEEE Electron Device Letters, vol. 29, no. 7, pp. 731–733, 2008.
11. S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Letters, vol. 8, no. 2, pp. 405–410,
2008.
12. H. Nathanson, W. Newell, R. Wickstro, and J. Davis, “Resonant gate transistor,”
IEEE Transactions on Electron Devices, vol. ED-14, no. 3, pp. 117–133, 1967.
13. A.M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M.J. Declercq, P. Renaud, C. Hilbert,
P. Fluckiger, and G.A. Racine, “Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture,” in
Proceedings of the International Symposium on Quality Electronic Design, pp. 496–501,
2002.
14. H. Kam, D.T. Lee, R.T. Howe, and T.-J. King, “A new nano-electro-mechanical
field effect transistor (NEMFET) design for low-power electronics,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 463–466, 2005.
15. A.M. Ionescu, K. Boucart, K.E. Moselund, V. Pott, and D. Tsamados, “Small
slope micro/nano-electronic switches,” in Proceedings of the International
Semiconductor Conference, pp. 397–402, 2007.
16. A.C. Seabaugh and Q. Zhang, “Low voltage tunnel transistors for beyond
CMOS logic,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2095–2110, 2010.
17. C. Zener, “A theory of the electrical breakdown of solid dielectrics,” Proceedings
of the Royal Society of London, vol. A145, no. 8555, pp. 523–529, 1934.
18. Y. Lu, A. Seabaugh, P. Fay, S.J. Koester, S.E. Laux, W. Haensch, and S.O. Koswatta,
“Geometry dependent tunnel FET performance-dilemma of electrostatics vs.
quantum confinement,” in Device Research Conference, pp. 17–18, 2010.
19. C. Hu, “Green transistor as a solution to the IC power crisis,” in 9th International
Conference on Solid-State and Integrated-Circuit Technology, pp. 16–20, 2008.
20. O.M. Stuetzer, “Junction fieldistors,” Proceedings of the IRE, vol. 40, no. 11,
pp. 1377–1381, 1952.
21. L. Esaki, “New phenomenon in narrow germanium p-n junctions,” Physical
Reviews, vol. 109, no. 2, pp. 603–604, 1958.
22. J. Quinn, G. Kawamoto, and B. McCombe, “Subband spectroscopy by surface
channel tunneling,” Surface Science, vol. 73, no. 1, pp. 190–196, 1978.
23. J.P. Leburton, J. Kolodzey, and S. Biggs, “Bipolar tunneling field-effect transistor: A three-terminal negative differential resistance device for high-speed
applications,” Applied Physics Letters, vol. 52, no. 9, pp. 1608–1620, 1988.