506
References
79. L. Ge and J.G. Fossum, “Analytical modeling of quantization and volume inversion in thin Si-film double gate MOSFETs,” IEEE Transactions on Electron Devices,
vol. 49, no. 2, pp. 287–294, 2002.
80. S. Venugopalan, M.A. Karim, S. Salahuddin, A.M. Niknejad, and C. Hu,
“Phenomenological compact model for QM charge centroid in multi gate
FETs,” IEEE Transactions on Electron Devices, vol. 60, no. 4, pp. 480–484, 2013.
81. D. Lu, “Compact models for future generation CMOS,” PhD dissertation,
Electrical Engineering and Computer Science, University of Berkeley, Berkeley,
CA, 2011.
82. S. Khandelwal, Y.S. Chauhan, D.D. Lu, S. Venugopalan, M.A.U. Karim, A.B.
Sachid, B.-Y. Nguyen, O. Rozeau, O. Faynot, A.M. Niknejad, and C.C. Hu,
“BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with backgate control,” IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2019–
2026, 2012.
83. Q. Chen, X. Zhong, Y. Wu, N. Zhu, W. Huang, D. Lu, C. Hu, B.Y. Nguyen, and
O. Faynot, “An exercise of ET/UTBB SOI CMOS modeling and simulation with
BSIM-IMG,” in Proceedings of the IEEE International SOI Conference, pp. 1–2, 2011.
84. D.E. Ward and R.W. Dutton, “A charge-oriented model for MOS transistor
capacitances,” IEEE Journal of Solid-State Circuits, vol. 13, no. 5, pp. 703–710, 1978.
85. S.Y. Oh, D.E. Ward, and R.W. Dutton, “Transient analysis of MOS transistors,”
IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 636–643, 1980.
Chapter 10
1. P.M. Solomon, “Device Proposals for Beyond Silicon CMOS,” IBM Research
Report RC24963, pp. 1–14. http://domino.watson.ibm.com/library/cyberdig.
nsf/papers/C12D0D2E53FE8833852576F90055CF7E/$File/rc24963.pdf, accessed
March 19, 2010.
2. K. Galatsis, A. Khitun, R. Ostroumov, K.L. Wang, W.R. Dichtel, E. Plummer,
J.F. Stoddart, J.I. Zink, J.Y. Lee, Y.-H. Xie, and K.W. Kim, “Alternate state variables
for emerging nanoelectronic devices,” IEEE Transactions on Nanotechnology, vol. 9,
no. 1, pp. 66–75, 2009.
3. A. Chen, A.P. Jacob, C.Y. Sung, K.L. Wang, A. Khitun, and W. Porod, “Collectiveeffect state variables for post-CMOS logic applications,” in Symposium on VLSI
Technology, pp. 132–133, 2009.
4. P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weiss, D. SchmittLandsiedel, and W. Hansch, “Complementary tunneling transistor for low power
application,” Solid-State Electronics, vol. 48, no. 12, pp. 2281–2286, 2004.
5. K.K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical
tunnel field-effect transistor with SiGe in the δp+ layer,” Japan Journal of Applied
Physics, vol. 43, no. 7R, pp. 4073–4078, 2004.
6. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in
carbon nanotube field-effect transistors,” Physical Review Letters, vol. 93, no. 19,
pp. 196805-1–196805-4, 2004.
References
79. L. Ge and J.G. Fossum, “Analytical modeling of quantization and volume inversion in thin Si-film double gate MOSFETs,” IEEE Transactions on Electron Devices,
vol. 49, no. 2, pp. 287–294, 2002.
80. S. Venugopalan, M.A. Karim, S. Salahuddin, A.M. Niknejad, and C. Hu,
“Phenomenological compact model for QM charge centroid in multi gate
FETs,” IEEE Transactions on Electron Devices, vol. 60, no. 4, pp. 480–484, 2013.
81. D. Lu, “Compact models for future generation CMOS,” PhD dissertation,
Electrical Engineering and Computer Science, University of Berkeley, Berkeley,
CA, 2011.
82. S. Khandelwal, Y.S. Chauhan, D.D. Lu, S. Venugopalan, M.A.U. Karim, A.B.
Sachid, B.-Y. Nguyen, O. Rozeau, O. Faynot, A.M. Niknejad, and C.C. Hu,
“BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with backgate control,” IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2019–
2026, 2012.
83. Q. Chen, X. Zhong, Y. Wu, N. Zhu, W. Huang, D. Lu, C. Hu, B.Y. Nguyen, and
O. Faynot, “An exercise of ET/UTBB SOI CMOS modeling and simulation with
BSIM-IMG,” in Proceedings of the IEEE International SOI Conference, pp. 1–2, 2011.
84. D.E. Ward and R.W. Dutton, “A charge-oriented model for MOS transistor
capacitances,” IEEE Journal of Solid-State Circuits, vol. 13, no. 5, pp. 703–710, 1978.
85. S.Y. Oh, D.E. Ward, and R.W. Dutton, “Transient analysis of MOS transistors,”
IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 636–643, 1980.
Chapter 10
1. P.M. Solomon, “Device Proposals for Beyond Silicon CMOS,” IBM Research
Report RC24963, pp. 1–14. http://domino.watson.ibm.com/library/cyberdig.
nsf/papers/C12D0D2E53FE8833852576F90055CF7E/$File/rc24963.pdf, accessed
March 19, 2010.
2. K. Galatsis, A. Khitun, R. Ostroumov, K.L. Wang, W.R. Dichtel, E. Plummer,
J.F. Stoddart, J.I. Zink, J.Y. Lee, Y.-H. Xie, and K.W. Kim, “Alternate state variables
for emerging nanoelectronic devices,” IEEE Transactions on Nanotechnology, vol. 9,
no. 1, pp. 66–75, 2009.
3. A. Chen, A.P. Jacob, C.Y. Sung, K.L. Wang, A. Khitun, and W. Porod, “Collectiveeffect state variables for post-CMOS logic applications,” in Symposium on VLSI
Technology, pp. 132–133, 2009.
4. P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weiss, D. SchmittLandsiedel, and W. Hansch, “Complementary tunneling transistor for low power
application,” Solid-State Electronics, vol. 48, no. 12, pp. 2281–2286, 2004.
5. K.K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical
tunnel field-effect transistor with SiGe in the δp+ layer,” Japan Journal of Applied
Physics, vol. 43, no. 7R, pp. 4073–4078, 2004.
6. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band tunneling in
carbon nanotube field-effect transistors,” Physical Review Letters, vol. 93, no. 19,
pp. 196805-1–196805-4, 2004.