504
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57. H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9, no. 10,
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59. Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain current model
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References
46. K. Fujita, Y. Torii, M. Hori, J. Oh, L. Shifren, P. Ranade, M. Nakagawa, K. Okabe,
T. Miyake, K. Ohkoshi, M. Kuramae, T. Mori, T. Tsuruta, S. Thompson, and
T. Ema, “Advanced channel engineering achieving aggressive reduction of
VT variation for ultra-low-power applications,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 32.3.1–32.3.4, December 2011.
47. S.K. Saha, “Transistors structure and method with an epitaxial layer over multiple halo implants,” US Patent Application 14/229,102, 2014.
48. R. Merritt, Intel’s FinFETs Approach Draws Fire from Rivals, 2012. http://www.eetimes
.com/electronicsnews/4403320/Fur-_ies-over-FinFETs-and-future-in-IEDM-panel,
accessed December 13, 2012.
49. T. Tanaka, H. Horie, S. Ando, and S. Hijiya, “Analysis of p/sup+ poly Si double-gate
thin-film SOI MOSFETs,” in IEEE International Electron Devices Meeting Technical
Digest, pp. 683–686, 1991.
50. N. Paydavosi, S. Venugopalan, Y.S. Chauhan, J.P. Duarte, S. Jandhyala, A.
Niknejad, and C.C. Hu, “BSIM—SPICE models enable FinFET and UTB IC
design,” IEEE Access, vol. 1, pp. 201–2016, 2013.
51. C. Maleville, Wafers for Fully Depleted Soi Devices: Ready for Volume Advanced Subs
trate News, 2010. http://www.advancedsubstratenews.com/2010/12/wafers-forfully-depleted-soi-devices-ready-for-volume/, accessed December 8, 2010.
52. Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, “Ultra-thin body PMOSFETs with selectively deposited Ge source/drain,” in Symposium on VLSI Technology, pp. 19–20,
2001.
53. H. Fang, S. Chuang, T. Chia Chang, K. Takei, T. Takahashi, and A. Javey, “Highperformance single layered WSe2 p-FETs with chemically doped contacts,”
Nano Letters, vol. 12, no. 7, pp. 3788–3792, 2012.
54. F. Andrieu et al., “Low leakage and low variability ultra-thin body and buried
oxide (UT2B) SOI technology for 20 nm low power CMOS and beyond,” in VLSI
Symposium on VLSI Technology, pp. 57–58, 2010.
55. Q. Liu et al., “Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond,” in Symposium on VLSI Technology, pp. 61–62,
2010.
56. K. Cheng et al., “ETSOI CMOS for system-on-chip applications featuring 22 nm
gate length, sub-100 nm gate pitch, and 0.08 μm 2 SRAM cell,” in Symposium on
VLSI Technology, pp. 128–129, 2011.
57. H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9, no. 10,
pp. 927–937, 1966.
58. J. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A.S. Roy, and C. Enz,
“A design oriented charge-based current model for symmetric DG MOSFET
and its correlation with the EKV formalism,” Solid-State Electronics, vol. 49, no. 3,
pp. 485–489, 2005.
59. Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain current model
for DG MOSFETs,” IEEE Electron Device Letters, vol. 25, no. 2, pp. 107–109, 2004.
60. M.V. Dunga, C.-H. Lin, X. Xi, D.D. Lu, A.M. Niknejad, and C. Hu, “Modeling
advanced FET technology in a compact model,” IEEE Transactions on Electron
Devices, vol. 53, no. 9, pp. 1971–1978, 2006.
61. M.V. Dunga, “Nanoscale CMOS modeling,” PhD dissertation, Electrical
Engineering and Computer Science, University of Berkeley, Berkeley, CA, 2008.