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K. Tsu-Jae, J. Bokor, and C. Hu, “A folded-channel MOSFET for deep-sub-tenth
micron era,” in IEEE International Electron Devices Meeting (IEDM) Technical Digest,
pp. 1032–1034, 1998.
31. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson,
H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.J. King, J. Bokor, and C.
Hu, “Sub 50-nm FinFET: PMOS,” in IEEE International Electron Devices Meeting
(IEDM) Technical Digest, pp. 67–70, 1999.
32. B. Yu, L. Chang, S. Ahmed, W. Haihong, S. Bell, C.-Y. Yang, C. Tabery, H. Chau,
X. Qi, K. Tsu-Jae, J. Bokor, C. Hu, L. Ming-Ren, and D. Kyser, “FinFET scaling
to 10 nm gate length,” in IEEE International Electron Devices Meeting Technical
Digest, pp. 251–254, 2002.
33. C. Jahan, O. Faynot, and M. Cassé, “Omega FETs transistors with TiN metal
gate and HfO2 down to 10nm,” in Symposium on VLSI Technology, pp. 112–113,
2005.
34. F.-L. Yang et al., “5 nm-gate nanowire FinFET,” in Symposium on VLSI Technology,
pp. 196–197, 2004.
35. H. Lee et al., “Sub-5 nm all around gate FinFET for ultimate scaling,” in
Symposium on VLSI Technology, pp. 58–59, 2006.
36. B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy,
R. Rios, and R. Chau, “High performance full depleted tri-gate CMOS transistors,”
IEEE Electron Device Letters, vol. 24, no. 4, pp. 263–265, 2003.
37. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,
“Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron
Device Letters, vol. 21, no. 5, pp. 254–255, 2000.
38. V. Barral et al., “Strained FDSOI CMOS technology scalability down to 2.5nm
_lm thickness and 18nm gate length with a TiN/HfO2 gate stack,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 61–64, 2011.
39. K. Cheng et al., “Fully depleted extremely thin SOI technology fabricated by a
novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain,” in Symposium on VLSI Technology, pp. 212–213,
2009.
40. O. Faynot et al., “Planar fully depleted SOI technology: A powerful architecture
for the 20nm node and beyond,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 51–53, 2010.
41. C. Auth, “22-nm fully-depleted tri-gate CMOS transistors,” in Proceedings of the
IEEE Custom Integrated Circuits Conference, pp. 1–6, 2012.
42. J. Markoff, Intel Increases Transistor Speed by Building Upward, 2011. http://www
.nytimes.com/2011/05/05/science/05chip.html, accessed May 4, 2014.
43. R. Merritt, TSMC taps ARM’s V8 on road to 16-nm FinFET, 2012. http://www
.eetimes.com/electronicsnews/4398727/ TSMC- taps-ARM-V8-in-road-to- 16-nmFinFET, accessed October 16, 2012.
44. D. McGrath, Globalfoundries Looks to Leapfrog Fab Rival, 2012. http://www. eetimes
. com/electronicsnews/4396720/ Globalfoundries-to-offer-14-nm- process-withFinFETfinn-2014, accessed September 20, 2012.
45. J.P. Noel, O. Thomas, M. Jaud, O. Weber, T. Poiroux, C. Fenouillet-Beranger,
P. Rivallin, P. Scheiblin, F. Andrieu, M. Vinet, O. Rozeau, F. Boeuf, O. Faynot, and
A. Amara, “Multi-VT UTBB FDSOI device architectures for low-power CMOS
circuit,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2473–2482, 2011.