502
References
14. S.K. Saha, “Method for forming channel-region doping profile for semiconductor device,” US Patent 6,323,520, November 27, 2001.
15. S.K. Saha, “Drain profile engineering for MOSFET devices with channel
lengths below 100 nm,” in Proceedings of the SPIE Conference on Microelectronic
Device Technology, vol. 3881, pp. 195–204, 1999.
16. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6,344,405, February 5, 2002.
17. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
18. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
19. S. Saha, “Device characteristics of sub-20-nm silicon nanotransistors,”
in Proceedings of the SPIE Conference on Design and Process Integration for
Microelectronic Manufacturing, vol. 5042, pp. 172–179, 2003.
20. M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie, G. Wang, R. Loo,
E. Simoen, J. Mitard, B. De Jaeger, G. Hellings, K. De Meyer, M. Meuris, and M.
Heyns, “Germanium for advanced CMOS anno 2009: A SWOT analysis,” in
IEEE International Electron Devices Meeting Technical Digest, pp. 1–4, 2009.
21. M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M.K. Hudait,
J.M. Fastenau, J. Kavalieros, W.K. Liu, D. Lubyshev, M. Metz, K. Millard,
N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, “Advanced high-K gate
diel ectric for high-performance short-channel In0.7Ga0.3As quantum well field
effect transistors on silicon substrate for low power logic applications,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 1–4, 2009.
22. F. Schwierz, “Graphene transistors,” National Nanotechnology, vol. 5, pp. 487–496,
2010.
23. B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis, “Single-layer
MoS2 transistors,” National Nanotechnology, vol. 6, no. 3, pp. 147–150, 2011.
24. J. Kanghoon, L. Wei-Yip, P. Patel, K. Chang Yong, O. Jungwoo, A. Bowonder,
P. Chanro, C.S. Park, C. Smith, P. Majhi, T. Hsing-Huang, R. Jammy, L. Tsu-Jae
King, and H. Chenming, “Si tunnel transistors with a novel silicided source and
46mV/dec swing,” in Symposium on VLSI Technology, pp. 121–122, 2010.
25. A.I. Khan, D. Bhowmik, P. Yu, S. Joo Kim, X. Pan, R. Ramesh, and S. Salahuddin,
“Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures,” Applied Physics Letters, vol. 99, no. 11, pp. 113501-1–113501-3,
2011.
26. M. Radosavljevic et al., “Electrostatics improvement in 3-D tri-gate over ultrathin body planar InGaAs quantum well field effect transistors with high-K
gate dielectric and scaled gate-to-drain/gate-to-source separation,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 765–768, 2011.
27. K. Tomioka, M. Yoshimura, and T. Fukui, “Steep-slope tunnel field-effect transistors using III–V nanowire/si-heterojunction,” in Symposium on VLSI Technology,
pp. 47–48, 2012.
28. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
29. C. Auth et al., “A 22-nm-high performance and low-power CMOS technology
featuring fully-depleted tri-gate transistors, self-aligned contacts and high density
MIM capacitors,” in Symposium on VLSI Technology, pp. 131–132, 2012.
References
14. S.K. Saha, “Method for forming channel-region doping profile for semiconductor device,” US Patent 6,323,520, November 27, 2001.
15. S.K. Saha, “Drain profile engineering for MOSFET devices with channel
lengths below 100 nm,” in Proceedings of the SPIE Conference on Microelectronic
Device Technology, vol. 3881, pp. 195–204, 1999.
16. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6,344,405, February 5, 2002.
17. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
18. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
19. S. Saha, “Device characteristics of sub-20-nm silicon nanotransistors,”
in Proceedings of the SPIE Conference on Design and Process Integration for
Microelectronic Manufacturing, vol. 5042, pp. 172–179, 2003.
20. M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie, G. Wang, R. Loo,
E. Simoen, J. Mitard, B. De Jaeger, G. Hellings, K. De Meyer, M. Meuris, and M.
Heyns, “Germanium for advanced CMOS anno 2009: A SWOT analysis,” in
IEEE International Electron Devices Meeting Technical Digest, pp. 1–4, 2009.
21. M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M.K. Hudait,
J.M. Fastenau, J. Kavalieros, W.K. Liu, D. Lubyshev, M. Metz, K. Millard,
N. Mukherjee, W. Rachmady, U. Shah, and R. Chau, “Advanced high-K gate
diel ectric for high-performance short-channel In0.7Ga0.3As quantum well field
effect transistors on silicon substrate for low power logic applications,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 1–4, 2009.
22. F. Schwierz, “Graphene transistors,” National Nanotechnology, vol. 5, pp. 487–496,
2010.
23. B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis, “Single-layer
MoS2 transistors,” National Nanotechnology, vol. 6, no. 3, pp. 147–150, 2011.
24. J. Kanghoon, L. Wei-Yip, P. Patel, K. Chang Yong, O. Jungwoo, A. Bowonder,
P. Chanro, C.S. Park, C. Smith, P. Majhi, T. Hsing-Huang, R. Jammy, L. Tsu-Jae
King, and H. Chenming, “Si tunnel transistors with a novel silicided source and
46mV/dec swing,” in Symposium on VLSI Technology, pp. 121–122, 2010.
25. A.I. Khan, D. Bhowmik, P. Yu, S. Joo Kim, X. Pan, R. Ramesh, and S. Salahuddin,
“Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures,” Applied Physics Letters, vol. 99, no. 11, pp. 113501-1–113501-3,
2011.
26. M. Radosavljevic et al., “Electrostatics improvement in 3-D tri-gate over ultrathin body planar InGaAs quantum well field effect transistors with high-K
gate dielectric and scaled gate-to-drain/gate-to-source separation,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 765–768, 2011.
27. K. Tomioka, M. Yoshimura, and T. Fukui, “Steep-slope tunnel field-effect transistors using III–V nanowire/si-heterojunction,” in Symposium on VLSI Technology,
pp. 47–48, 2012.
28. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
29. C. Auth et al., “A 22-nm-high performance and low-power CMOS technology
featuring fully-depleted tri-gate transistors, self-aligned contacts and high density
MIM capacitors,” in Symposium on VLSI Technology, pp. 131–132, 2012.