501
References
58. J.D. Plummer, M.D. Deal, and P.B. Griffin, Silicon VLSI Technology: Fundamentals,
Practice and Modeling, Prentice Hall, Upper Saddle River, NJ, 2000.
59. S.K. Saha, “Transistors structure and method with an epitaxial layer over multiple halo implants,” US Patent Application 14/229,102, 2014.
60. J.-P. Colinge, (ed.), FinFETs and Other Multi-Gate Transistors. Springer, New York,
2008.
Chapter 9
1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo,
E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned doublegate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47,
no. 12, pp. 2320–2325, 2000.
2. H.-S.P. Wong, D.J. Frank, P.M. Solomon, and Y. Taur, “Device design considerations for double gate, ground plane, and single-gate ultra-thin SOI MOSFETs
at the 25 nm channel length generation,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 407–410, 1998.
3. G. Bertrand, S. Deleonibus, B. Previtali, G. Guegan, X. Jehl, M. Sanquer, and
F. Balestra, “Toward the limits of conventional MOSFETs: Case of sub 30 nm
NMOS devices,” Solid-State Electronics, vol. 48, no. 4, pp. 505–509, 2004.
4. D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, and H.-S.
PhilipWong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of the IEEE, vol. 89, no. 3, pp. 259–288, 2001.
5. Y. Taur, D.A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, S.-H. Lo, G.A. SaiHalasz, R.G. Viswanathan, H.-J.C. Wann, S.J. Wind, and H.-S. Wong, “CMOS
scaling into the nanometer regime,” Proceedings of the IEEE, vol. 85, no. 4,
pp. 486–504, 1997.
6. K.J. Kuhn, “Moore’s law past 32nm: Future challenges in device scaling,” in
13th International Workshop on Computer Electronics, pp. 1–6, 2009.
7. C. Hu, Modern Semiconductor Devices for Integrated Circuits, 1st edition, Pearson
Education, Upper Saddle River, NJ, 2010.
8. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
9. K.J. Kuhn, M.D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S.T. Ma,
A. Maheshwari, and S. Mudanai, “Process technology variation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2197–2208, 2011.
10. L.D. Yau, “A simple theory to predict the threshold voltage of short-channel
IGFET’s,” Solid-State Electronics, vol. 17, no. 10, pp. 1059–1063, 1974.
11. Z.H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, J. Min-Chie, P.K. Ko, and Y.C.
Cheng, “Threshold voltage model for deep-submicrometer MOSFETs,” IEEE
Transactions, vol. 40, no. 1, pp. 86–95, 1993.
12. R.R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE
Journal of Solid-State Circuits, vol. 14, no. 2, pp. 383–391, 1979.
13. S. Saha, “Effects of inversion layer quantization on channel profile engineering
for nMOSFETs with 0.1 μm channel lengths,” Solid-State Electronics, vol. 42,
no. 11, pp. 1985–1991, 1998.
References
58. J.D. Plummer, M.D. Deal, and P.B. Griffin, Silicon VLSI Technology: Fundamentals,
Practice and Modeling, Prentice Hall, Upper Saddle River, NJ, 2000.
59. S.K. Saha, “Transistors structure and method with an epitaxial layer over multiple halo implants,” US Patent Application 14/229,102, 2014.
60. J.-P. Colinge, (ed.), FinFETs and Other Multi-Gate Transistors. Springer, New York,
2008.
Chapter 9
1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo,
E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned doublegate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47,
no. 12, pp. 2320–2325, 2000.
2. H.-S.P. Wong, D.J. Frank, P.M. Solomon, and Y. Taur, “Device design considerations for double gate, ground plane, and single-gate ultra-thin SOI MOSFETs
at the 25 nm channel length generation,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 407–410, 1998.
3. G. Bertrand, S. Deleonibus, B. Previtali, G. Guegan, X. Jehl, M. Sanquer, and
F. Balestra, “Toward the limits of conventional MOSFETs: Case of sub 30 nm
NMOS devices,” Solid-State Electronics, vol. 48, no. 4, pp. 505–509, 2004.
4. D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, and H.-S.
PhilipWong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of the IEEE, vol. 89, no. 3, pp. 259–288, 2001.
5. Y. Taur, D.A. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, S.-H. Lo, G.A. SaiHalasz, R.G. Viswanathan, H.-J.C. Wann, S.J. Wind, and H.-S. Wong, “CMOS
scaling into the nanometer regime,” Proceedings of the IEEE, vol. 85, no. 4,
pp. 486–504, 1997.
6. K.J. Kuhn, “Moore’s law past 32nm: Future challenges in device scaling,” in
13th International Workshop on Computer Electronics, pp. 1–6, 2009.
7. C. Hu, Modern Semiconductor Devices for Integrated Circuits, 1st edition, Pearson
Education, Upper Saddle River, NJ, 2010.
8. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
9. K.J. Kuhn, M.D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S.T. Ma,
A. Maheshwari, and S. Mudanai, “Process technology variation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2197–2208, 2011.
10. L.D. Yau, “A simple theory to predict the threshold voltage of short-channel
IGFET’s,” Solid-State Electronics, vol. 17, no. 10, pp. 1059–1063, 1974.
11. Z.H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, J. Min-Chie, P.K. Ko, and Y.C.
Cheng, “Threshold voltage model for deep-submicrometer MOSFETs,” IEEE
Transactions, vol. 40, no. 1, pp. 86–95, 1993.
12. R.R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE
Journal of Solid-State Circuits, vol. 14, no. 2, pp. 383–391, 1979.
13. S. Saha, “Effects of inversion layer quantization on channel profile engineering
for nMOSFETs with 0.1 μm channel lengths,” Solid-State Electronics, vol. 42,
no. 11, pp. 1985–1991, 1998.