500
References
41. I. Ahsan et al., “RTA-driven intradie variations in stage delay and parametric sensitivities for 65-nm technology,” in Symposium on VLSI Technology, pp. 170–171, 2006.
42. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching properties of
MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433–1439,
1989.
43. M. Pelgrom, H. Tuinhout, and M. Vertregt, “Modeling of MOS Matching,” in
Compact Modeling: Principles, Techniques and Applications, G. Gildenblat, (ed.)
Springer, London, 2010.
44. J. Mazurier, O. Weber, F. Andrieu, A. Toffoli, O. Rozeau, T. Poiroux, F. Allain,
P. Perreau, C. Fenouillet-Beranger, O. Thomas, M. Belleville, and O. Faynot,
“On the variability in planar FDSOI technology: From MOSFETs to SRAM
cells,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2326–2336, 2011.
45. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu,
K. cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, and C. Hu, “BSIM4v4.8.0 MOSFET
Model User’s Manual,” University of California, Berkeley, CA, 2013.
46. N.D. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
47. J.A. Croon, W. Sansen, and H.E. Maes, “Matching properties of deep sub-micron
MOS transistors,” Springer, Amsterdam, the Netherlands, 2005.
48. K. Fujita, Y. Tori, M. Hori, J. Oh, L. Shifren, P. Ranade, M. Nakagawa, K. Okabe, T.
Miyake, K. Ohkoshi, M. Kuramae, T. Mori, T. Tsuruta, S. Thompson, and T. Ema,
“Advanced channel engineering achieving aggressive reduction of VT variation
for ultra-low-power applications,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 749–752, 2011.
49. S. Saha, “Effects of inversion layer quantization on channel profile engineering
for nMOSFETs with 0.1 μm channel lengths,” Solid-State Electronics, vol. 42, no. 11,
pp. 1985–1991, 1998.
50. S.K. Saha, “Method for forming channel-region doping profile for semiconductor device,” US Patent 6,323,520, November 2001.
51. S. Saha, C.S. Yeh, and B. Gadepally, “Impact ionization rate of electrons for
accurate simulation of substrate current in submicron devices,” Solid-State
Electronics, vol. 36, no. 10, pp. 1429–1432, 1993.
52. S. Saha, “Extraction of substrate current model parameters from device simulation,” Solid-State Electronics, vol. 37, no. 10, pp. 1786–1788, 1994.
53. S.K. Saha, “Introduction to technology computer aided design,” in Technology
Computer Aided Design: Simulation for VLSI MOSFET: C.K. Sarkar, (ed.). CRC
Press, Boca Raton, FL, 2013.
54. S.K. Saha, “Modelling the effectiveness of computer-aided development
projects in the semiconductor industry,” International Journal of Engineering
Management and Economics, vol. 1, no. 2/3, pp. 162–178, 2010.
55. S.K. Saha, “Managing technology CAD for competitive advantage: An efficient
approach for integrated circuit fabrication technology development,” IEEE
Transactions on Engineering and Management, vol. 46, no. 2, pp. 221–229, 1999.
56. Synopsys Inc., HSPICE User Guide: Simulation and Analysis, B-2008.09, Synopsys
Inc., September 2008.
57. M. Kanno, A. Shibuya, M. Matsumura, K. Tamura, H. Tsuno, S. Mori, Y. Fukuzaki,
T. Gocho, H. Ansai, and N. Nagashima, “Empirical characteristics and extraction
of overall variations for 65-nm MOSFETs and beyond,” in Symposium on VLSI
Technology, pp. 88–89, 2007.
References
41. I. Ahsan et al., “RTA-driven intradie variations in stage delay and parametric sensitivities for 65-nm technology,” in Symposium on VLSI Technology, pp. 170–171, 2006.
42. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching properties of
MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433–1439,
1989.
43. M. Pelgrom, H. Tuinhout, and M. Vertregt, “Modeling of MOS Matching,” in
Compact Modeling: Principles, Techniques and Applications, G. Gildenblat, (ed.)
Springer, London, 2010.
44. J. Mazurier, O. Weber, F. Andrieu, A. Toffoli, O. Rozeau, T. Poiroux, F. Allain,
P. Perreau, C. Fenouillet-Beranger, O. Thomas, M. Belleville, and O. Faynot,
“On the variability in planar FDSOI technology: From MOSFETs to SRAM
cells,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2326–2336, 2011.
45. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu,
K. cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, and C. Hu, “BSIM4v4.8.0 MOSFET
Model User’s Manual,” University of California, Berkeley, CA, 2013.
46. N.D. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
47. J.A. Croon, W. Sansen, and H.E. Maes, “Matching properties of deep sub-micron
MOS transistors,” Springer, Amsterdam, the Netherlands, 2005.
48. K. Fujita, Y. Tori, M. Hori, J. Oh, L. Shifren, P. Ranade, M. Nakagawa, K. Okabe, T.
Miyake, K. Ohkoshi, M. Kuramae, T. Mori, T. Tsuruta, S. Thompson, and T. Ema,
“Advanced channel engineering achieving aggressive reduction of VT variation
for ultra-low-power applications,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 749–752, 2011.
49. S. Saha, “Effects of inversion layer quantization on channel profile engineering
for nMOSFETs with 0.1 μm channel lengths,” Solid-State Electronics, vol. 42, no. 11,
pp. 1985–1991, 1998.
50. S.K. Saha, “Method for forming channel-region doping profile for semiconductor device,” US Patent 6,323,520, November 2001.
51. S. Saha, C.S. Yeh, and B. Gadepally, “Impact ionization rate of electrons for
accurate simulation of substrate current in submicron devices,” Solid-State
Electronics, vol. 36, no. 10, pp. 1429–1432, 1993.
52. S. Saha, “Extraction of substrate current model parameters from device simulation,” Solid-State Electronics, vol. 37, no. 10, pp. 1786–1788, 1994.
53. S.K. Saha, “Introduction to technology computer aided design,” in Technology
Computer Aided Design: Simulation for VLSI MOSFET: C.K. Sarkar, (ed.). CRC
Press, Boca Raton, FL, 2013.
54. S.K. Saha, “Modelling the effectiveness of computer-aided development
projects in the semiconductor industry,” International Journal of Engineering
Management and Economics, vol. 1, no. 2/3, pp. 162–178, 2010.
55. S.K. Saha, “Managing technology CAD for competitive advantage: An efficient
approach for integrated circuit fabrication technology development,” IEEE
Transactions on Engineering and Management, vol. 46, no. 2, pp. 221–229, 1999.
56. Synopsys Inc., HSPICE User Guide: Simulation and Analysis, B-2008.09, Synopsys
Inc., September 2008.
57. M. Kanno, A. Shibuya, M. Matsumura, K. Tamura, H. Tsuno, S. Mori, Y. Fukuzaki,
T. Gocho, H. Ansai, and N. Nagashima, “Empirical characteristics and extraction
of overall variations for 65-nm MOSFETs and beyond,” in Symposium on VLSI
Technology, pp. 88–89, 2007.