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36. J. Steigerwald, “Chemical mechanical polish: The enabling technology,” in
IEEE International Electron Devices Meeting Technical Digest, pp. 37–40, 2008.
37. Y.L. Tsang, S. Chattopadhyay, S. Uppal, E. Escobedo-Cousin, H.K. Ramakrishnan,
S.H. Olsen, and A.G. O’Neill, “Modeling of the threshold voltage in strained Si/
Si1−xGexSi1−yGex CMOS architectures,” IEEE Transactions on Electron Devices,
vol. 54, no. 11, pp. 3040–3048, 2007.
38. O. Weber et al., “High immunity to threshold voltage variability in undoped
ultrathin FDSOI MOSFETs and its physical understanding,” in IEEE International
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References
28. M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara,
K. Shibahara, S. Miyazaki, and M. Hirose, “Limit of gate oxide thickness scaling in
MOSFETs due to apparent threshold voltage fluctuation introduced by tunneling
leakage current,” IEEE Transactions on Electron Devices, vol. 48, no. 2, pp. 259–264,
2001.
29. A. Asenov, S. Kaya, and J.H. Davies, “Intrinsic threshold voltage fluctuations
in decananometer MOSFETs due to local oxide thickness variations,” IEEE
Transactions on Electron Devices, vol. 49, no. 1, pp. 112–119, 2002.
30. A.R. Brown, G. Roy, and A. Asenov, “Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture,” IEEE Transactions on
Electron Devices, vol. 54, no. 11, pp. 3056–3063, 2007.
31. Y. Zhang, J. Li, M. Grubbs, M. Deal, B. Magyari-Kope, B.M. Clemens, and Y. Nishi,
“Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 57–60, 2009.
32. V.S. Kaushik, B.J. O’Sullivan, G. Pourtois, N. Van Hoornick, A. Delabie, S. Van
Elshocht, W. Deweerd, T. Schram, L. Pantisano, E. Rohr, L.-A. Ragnarsson, S. De
Gendt, and M. Heyns, “Estimation of fixed charge densities in hafnium–silicate
gate dielectrics,” IEEE Transactions on Electron Devices, vol. 53, no. 10, pp. 2627–2633,
2006.
33. H.C. Wen, H.R. Harris, C.D. Young, H. Luan, H.N. Alshareef, K. Choi, D.-L. Kwong,
P. Majhi, G. Bersuker, and H. Lee, “On oxygen deficiency and fast transient
charge-trapping effects in high-k dielectrics,” IEEE Electron Device Letters, vol. 27,
no. 12, pp. 984–987, 2006.
34. L. Capodieci, “From optical proximity correction to lithography-driven physical
design (1996–2006): 10 years of resolution enhancement technology and the roadmap enablers for the next decade,” in Proceedings of the SPIE, vol. 6154, p. 615401,
2006.
35. S. Nag, A. Chatterjee, K. Taylor, I. Ali, S. O’Brien, S. Aur, J.D. Luttmer, and
I.C. Chen, “Comparative evaluation of gap-fill dielectrics in shallow trench
isolation for sub-0.25-μm technologies,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 841–845, 1996.
36. J. Steigerwald, “Chemical mechanical polish: The enabling technology,” in
IEEE International Electron Devices Meeting Technical Digest, pp. 37–40, 2008.
37. Y.L. Tsang, S. Chattopadhyay, S. Uppal, E. Escobedo-Cousin, H.K. Ramakrishnan,
S.H. Olsen, and A.G. O’Neill, “Modeling of the threshold voltage in strained Si/
Si1−xGexSi1−yGex CMOS architectures,” IEEE Transactions on Electron Devices,
vol. 54, no. 11, pp. 3040–3048, 2007.
38. O. Weber et al., “High immunity to threshold voltage variability in undoped
ultrathin FDSOI MOSFETs and its physical understanding,” in IEEE International
Electron Devices Meeting Technical Digest, pp. 245–248, 2008.
39. L.-T. Pang, K. Qian, C.J. Spanos, and B. Nikolic, “Measurement and analysis of
variability in 45-nm strained-Si CMOS technology,” IEEE Journal of Solid-State
Circuits, vol. 44, no. 8, pp. 2233–2243, 2009.
40. T. Tanaka, T. Usuki, T. Futatsugi, Y. Momiyama, and T. Sugii, “Vth fluctuation
induced by statistical variation of pocket dopant profile,” in IEEE International
Electron Devices Meeting Technical Digest, pp. 271–274, 2000.