498
References
12. K. Bernstein, D.J. Frank, A.E. Gattiker, W. Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak,
D.J. Pearson, and N.J. Rohrer, “High-performance CMOS variability in the 65-nm
regime and beyond,” IBM Journal of Research and Development vol. 50, no. 4/5,
pp. 433–449, 2006.
13. S.K. Springer, S. Lee, N. Lu, E.J. Nowak, J.O. Plouchart, J.S. Watts, R.Q. Williams,
and N. Zamder, “Modeling of variation in submicrometer CMOS ULSI technologies,” IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2168–2178, 2006.
14. K. Singhal and V. Visvanathan, “Statistical models for worst case files and
electrical data,” IEEE Transactions on Semiconductor Manufacturing, vol. 12,
no. 4, pp. 470–484, 1999.
15. S.M. Kang and A. Dharchoudhury, “Worst-case analysis and optimization of
VLSI circuit performances,” IEEE Transactions on Computer-Aided Design, vol. 14,
pp. 481–492, 1995.
16. I.N. Hajj, T.N. Trick, T.-K. Yu, and S.M. Kang, “Statistical performance modeling
and parametric yield estimation of MOS VLSI,” IEEE Transactions on ComputerAided Design, vol. CAD-6, pp. 1013–1022, 1987.
17. J.C. Chen, C. Hu, C.-P. Wan, P. Bendix, and A. Kapoor, “E-T based statistical
modeling and compact statistical circuit simulation methodologies,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 635–638, 1996.
18. C.-H. Lin, M.V. Dunga, D.D. Lu, A.M. Niknejad, and C. Hu, “Performance-aware
corner model for design for manufacturing,” IEEE Transactions on Electron
Devices, vol. 56, no. 4, pp. 595–600, 2009.
19. G. Rappitsch, E. Seebacher, M. Kocher, and E. Stadlober, “SPICE Modeling of
process variation using location depth corner models,” IEEE Transactions on
Semiconductor Manufacturing, vol. 17, no. 2, pp. 201–213, 2004.
20. C.C. McAndrew, “Statistical modeling for circuit simulation,” in Proceedings of
the International Symposium on Quality Electronic Design, pp. 496–501, 2003.
21. C.C. McAndrew, I. Stevanovic, X. Li, and G. Gildenblat, “Extensions to backward propagation of variance for statistical modeling,” IEEE Design & Test of
Computers, vol. 27, no. 2, pp. 36–43, 2010.
22. International Technology Roadmap for Semiconductors, ITRS 2012 updates,
http://www.itrs.net/reports.html, access date: June 9, 2015.
23. P. Stolk, F. Widdershoven, and D. Klaassen, “Modeling statistical dopant fluctuations in MOS transistors,” IEEE Transactions on Electron Devices, vol. 45, no. 9,
pp. 1960–1971, 1998.
24. T. Mizuno, J.-I. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs,”
IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 2216–2221, 1994.
25. A. Asenov, “Random-dopant-induced threshold voltage lowering and fluctuations in sub-0.1-μm MOSFETs: A 3-D ‘atomistic’ simulation study,” IEEE
Transactions on Electron Devices, vol. 45, no. 12, pp. 2505–2513, 1998.
26. A. Asenov, S. Kaya, and A.R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by line edge roughness,” IEEE Transactions on
Electron Devices, vol. 50, no. 5, pp. 1254–1260, 2003.
27. C.H. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young, “An experimentally validated analytical model for gate line edge roughness (LER) effects on technology scaling,” IEEE Electron Device Letters, vol. 22, no. 6, pp. 287–289, 2001.
References
12. K. Bernstein, D.J. Frank, A.E. Gattiker, W. Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak,
D.J. Pearson, and N.J. Rohrer, “High-performance CMOS variability in the 65-nm
regime and beyond,” IBM Journal of Research and Development vol. 50, no. 4/5,
pp. 433–449, 2006.
13. S.K. Springer, S. Lee, N. Lu, E.J. Nowak, J.O. Plouchart, J.S. Watts, R.Q. Williams,
and N. Zamder, “Modeling of variation in submicrometer CMOS ULSI technologies,” IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2168–2178, 2006.
14. K. Singhal and V. Visvanathan, “Statistical models for worst case files and
electrical data,” IEEE Transactions on Semiconductor Manufacturing, vol. 12,
no. 4, pp. 470–484, 1999.
15. S.M. Kang and A. Dharchoudhury, “Worst-case analysis and optimization of
VLSI circuit performances,” IEEE Transactions on Computer-Aided Design, vol. 14,
pp. 481–492, 1995.
16. I.N. Hajj, T.N. Trick, T.-K. Yu, and S.M. Kang, “Statistical performance modeling
and parametric yield estimation of MOS VLSI,” IEEE Transactions on ComputerAided Design, vol. CAD-6, pp. 1013–1022, 1987.
17. J.C. Chen, C. Hu, C.-P. Wan, P. Bendix, and A. Kapoor, “E-T based statistical
modeling and compact statistical circuit simulation methodologies,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 635–638, 1996.
18. C.-H. Lin, M.V. Dunga, D.D. Lu, A.M. Niknejad, and C. Hu, “Performance-aware
corner model for design for manufacturing,” IEEE Transactions on Electron
Devices, vol. 56, no. 4, pp. 595–600, 2009.
19. G. Rappitsch, E. Seebacher, M. Kocher, and E. Stadlober, “SPICE Modeling of
process variation using location depth corner models,” IEEE Transactions on
Semiconductor Manufacturing, vol. 17, no. 2, pp. 201–213, 2004.
20. C.C. McAndrew, “Statistical modeling for circuit simulation,” in Proceedings of
the International Symposium on Quality Electronic Design, pp. 496–501, 2003.
21. C.C. McAndrew, I. Stevanovic, X. Li, and G. Gildenblat, “Extensions to backward propagation of variance for statistical modeling,” IEEE Design & Test of
Computers, vol. 27, no. 2, pp. 36–43, 2010.
22. International Technology Roadmap for Semiconductors, ITRS 2012 updates,
http://www.itrs.net/reports.html, access date: June 9, 2015.
23. P. Stolk, F. Widdershoven, and D. Klaassen, “Modeling statistical dopant fluctuations in MOS transistors,” IEEE Transactions on Electron Devices, vol. 45, no. 9,
pp. 1960–1971, 1998.
24. T. Mizuno, J.-I. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs,”
IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 2216–2221, 1994.
25. A. Asenov, “Random-dopant-induced threshold voltage lowering and fluctuations in sub-0.1-μm MOSFETs: A 3-D ‘atomistic’ simulation study,” IEEE
Transactions on Electron Devices, vol. 45, no. 12, pp. 2505–2513, 1998.
26. A. Asenov, S. Kaya, and A.R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by line edge roughness,” IEEE Transactions on
Electron Devices, vol. 50, no. 5, pp. 1254–1260, 2003.
27. C.H. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young, “An experimentally validated analytical model for gate line edge roughness (LER) effects on technology scaling,” IEEE Electron Device Letters, vol. 22, no. 6, pp. 287–289, 2001.