497
References
55. S.H.M. Jen, C.C. Enz, D.R. Pehlke, M. Schroter, and B.J. Sheu, “Accurate modeling and parameter extraction for MOS transistor valid up to l0-GHz,” IEEE
Transactions on Electron Devices, vol. 46, no. 11, pp. 2217–2227, 1999.
56. R. Goyal, High-Frequency Analog Integrated Circuit Design, John Wiley & Sons,
New York, 1994.
57. W. Liu and M.-C. Chang, “Transistor transient studies including transcapacitive
current and distributive gate resistance for inverter circuits,” IEEE Transactions
on Circuit and Systems I: Fundamental Theory and Applications, vol. 45, no. 4,
pp. 416–422, 1998.
58. X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M.J. Deen, P.R. Gray, and C. Hu, “An effective
gate resistance model for CMOS RF and noise modeling,” in IEEE International
Electron Devices Meeting Technical Digest, pp. 961–964, 1998.
59. C. Enz and Y. Cheng, “MOS transistor modeling issues for RF circuit design,”
Workshop of Advances in Analog Circuit Design, Nice, France, March 1999.
Chapter 8
1. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
2. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc,
“Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE
Journal of Solid-State Circuits, vol. SC-9, no. 5, pp. 256–268, 1974.
3. H. Iwai, “CMOS technology—Year 2010 and beyond,” IEEE Journal of Solid-State
Circuits, vol. 34, no. 3, pp. 357–366, 1999.
4. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
5. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
6. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
7. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6,344,405, February 5, 2002.
8. S. Saha, “Device characteristics of sub-20 nm silicon nanotransistors,”
in Proceedings of the SPIE Conference on Design and Process Integration for
Microelectronic Manufacturing, vol. 5042, pp. 172–179, 2003.
9. S.K. Saha, “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 104–115, 2014.
10. K.J. Kuhn, M.D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S.T. Ma,
A. Maheshwari, and S. Mudanai, “Process technology variation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2197–2208, 2011.
11. C.M. Mezzomo, A. Bajolet, A. Cathignol, R. Di Frenza, and G. Ghibaudo,
“Characterization and modeling of transistor variability in advanced CMOS
technologies,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2235–2248,
2011.
References
55. S.H.M. Jen, C.C. Enz, D.R. Pehlke, M. Schroter, and B.J. Sheu, “Accurate modeling and parameter extraction for MOS transistor valid up to l0-GHz,” IEEE
Transactions on Electron Devices, vol. 46, no. 11, pp. 2217–2227, 1999.
56. R. Goyal, High-Frequency Analog Integrated Circuit Design, John Wiley & Sons,
New York, 1994.
57. W. Liu and M.-C. Chang, “Transistor transient studies including transcapacitive
current and distributive gate resistance for inverter circuits,” IEEE Transactions
on Circuit and Systems I: Fundamental Theory and Applications, vol. 45, no. 4,
pp. 416–422, 1998.
58. X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M.J. Deen, P.R. Gray, and C. Hu, “An effective
gate resistance model for CMOS RF and noise modeling,” in IEEE International
Electron Devices Meeting Technical Digest, pp. 961–964, 1998.
59. C. Enz and Y. Cheng, “MOS transistor modeling issues for RF circuit design,”
Workshop of Advances in Analog Circuit Design, Nice, France, March 1999.
Chapter 8
1. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
2. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R. LeBlanc,
“Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE
Journal of Solid-State Circuits, vol. SC-9, no. 5, pp. 256–268, 1974.
3. H. Iwai, “CMOS technology—Year 2010 and beyond,” IEEE Journal of Solid-State
Circuits, vol. 34, no. 3, pp. 357–366, 1999.
4. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
5. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
6. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
7. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6,344,405, February 5, 2002.
8. S. Saha, “Device characteristics of sub-20 nm silicon nanotransistors,”
in Proceedings of the SPIE Conference on Design and Process Integration for
Microelectronic Manufacturing, vol. 5042, pp. 172–179, 2003.
9. S.K. Saha, “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 104–115, 2014.
10. K.J. Kuhn, M.D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S.T. Ma,
A. Maheshwari, and S. Mudanai, “Process technology variation,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2197–2208, 2011.
11. C.M. Mezzomo, A. Bajolet, A. Cathignol, R. Di Frenza, and G. Ghibaudo,
“Characterization and modeling of transistor variability in advanced CMOS
technologies,” IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2235–2248,
2011.