495
References
21. K.K. Hung, P.K. Ko, C. Hu, and Y.C. Cheng, “A unified model for the flicker
noise in metal-oxide-semiconductor field-effect transistors,” IEEE Transactions
on Electron Devices, vol. 37, no. 3, pp. 654–665, 1990.
22. Z. Celik-Butler and T.Y. Hsiang, “Spectral dependence of 1/fγ noise on gate bias
in n-MOSFETs,” Solid-State Electronics, vol. 30, no. 4, pp. 419–423, 1987.
23. C. Surya, and T.Y. Hsiang, “Theory and experiments on the 1/f'γ noise in
p-channel metal-oxide-semiconductor field-effect transistors at low drain
bias,” Physics Review, vol. B33, no. 7, pp. 4898–4905, 1986.
24. L.K.J. Vandamme, “Model for l/f noise in MOS transistor based in linear
region,” Solid-State Electronics, vol. 23, no. 4, pp. 317–323, 1980.
25. R.P. Jindal and A. van der Ziel, “Phonon fluctuation model for flicker noise in
elemental semiconductor,” Journal of Applied Physics, vol. 52, no. 4, pp. 2884–2888,
1981.
26. H.S. Park, A. van der Ziel, and S.T. Liu, “Comparison of two l/f noise models in
MOSFETs,” Solid-State Electronics, vol. 25, no. 3, pp. 213–217, 1982.
27. S. Liu and L.W. Nagel, “Small signal MOSFET models for analog circuit design,”
IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 983–998, 1982.
28. Y. Cheng et al., BSIM3 version 3 User’s Manual, Memorandum No. UCBIERL
M97/2, University of California, Berkeley, CA, 1997.
29. K.K. Hung, P.K. Ko, C. Hu, and Y.C. Cheng, “A physics-based MOSFET noise
model for circuit simulation,” IEEE Transactions on Electron Devices, vol. 37, no. 5,
pp. 1323–1333, 1990.
30. G. Reimbold, “Modified l/f trapping noise theory and experiments in MOS
transistors biased from weak to strong inversion influence of interface state,”
IEEE Transactions on Electron Devices, vol. 31, no. 9, pp. 1190–1198, 1984.
31. S.C. Sun, and J.D. Plummer, “Electron mobility in inversion and accumulation
layers on thermally oxidized silicon surfaces,” IEEE Transactions on Electron
Devices, vol. 27, no. 8, pp. 1497–1508, 1980.
32. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu,
K. cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, and C. Hu, “BSIM4v4.8.0 MOSFET
Model User’s Manual,” University of California, Berkeley, CA, 2013.
33. J.J. Paulous and D.A. Antoniadis, “Limitations of quasi-static capacitance models
for the MOS transistors,” IEEE Electron Device Letters, vol. 4, no. 7, pp. 221–224,
1983.
34. S.Y. Oh, D.E. Ward, and R.W. Dutton, “Transient analysis of MOS transistors,”
IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 636–643, 1980.
35. M. Chan, K.Y. Hui, C. Hui, and P.K. Ko, “A robust and physical BSIM3 nonquasi-static transient and AC small signal model for circuit simulation,” IEEE
Transactions on Electron Devices, vol. 45, no. 4, pp. 834–841, 1998.
36. P. Yang and P.K. Chatterjee, “SPICE modeling for small geometry MOSFET circuits,” IEEE Transactions on Computer-Aided Design, vol. 1, no. 4, pp. 169–182,
1982.
37. Y.P. Tsividis and G. Masetti, “Problems in the precision modeling of the MOS
transistor for analog applications,” IEEE Transactions on Computer-Aided Design,
vol. 3, no. 1, pp. 72–79, 1984.
38. T.L. Quarles, SPICE 3 Implementation Guide, Memorandum No. UCB/ERL
M89/44, April 1989.
References
21. K.K. Hung, P.K. Ko, C. Hu, and Y.C. Cheng, “A unified model for the flicker
noise in metal-oxide-semiconductor field-effect transistors,” IEEE Transactions
on Electron Devices, vol. 37, no. 3, pp. 654–665, 1990.
22. Z. Celik-Butler and T.Y. Hsiang, “Spectral dependence of 1/fγ noise on gate bias
in n-MOSFETs,” Solid-State Electronics, vol. 30, no. 4, pp. 419–423, 1987.
23. C. Surya, and T.Y. Hsiang, “Theory and experiments on the 1/f'γ noise in
p-channel metal-oxide-semiconductor field-effect transistors at low drain
bias,” Physics Review, vol. B33, no. 7, pp. 4898–4905, 1986.
24. L.K.J. Vandamme, “Model for l/f noise in MOS transistor based in linear
region,” Solid-State Electronics, vol. 23, no. 4, pp. 317–323, 1980.
25. R.P. Jindal and A. van der Ziel, “Phonon fluctuation model for flicker noise in
elemental semiconductor,” Journal of Applied Physics, vol. 52, no. 4, pp. 2884–2888,
1981.
26. H.S. Park, A. van der Ziel, and S.T. Liu, “Comparison of two l/f noise models in
MOSFETs,” Solid-State Electronics, vol. 25, no. 3, pp. 213–217, 1982.
27. S. Liu and L.W. Nagel, “Small signal MOSFET models for analog circuit design,”
IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 983–998, 1982.
28. Y. Cheng et al., BSIM3 version 3 User’s Manual, Memorandum No. UCBIERL
M97/2, University of California, Berkeley, CA, 1997.
29. K.K. Hung, P.K. Ko, C. Hu, and Y.C. Cheng, “A physics-based MOSFET noise
model for circuit simulation,” IEEE Transactions on Electron Devices, vol. 37, no. 5,
pp. 1323–1333, 1990.
30. G. Reimbold, “Modified l/f trapping noise theory and experiments in MOS
transistors biased from weak to strong inversion influence of interface state,”
IEEE Transactions on Electron Devices, vol. 31, no. 9, pp. 1190–1198, 1984.
31. S.C. Sun, and J.D. Plummer, “Electron mobility in inversion and accumulation
layers on thermally oxidized silicon surfaces,” IEEE Transactions on Electron
Devices, vol. 27, no. 8, pp. 1497–1508, 1980.
32. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He, W. Liu,
K. cao, X. Jin, J.J. Ou, M. Chan, A.M. Niknejad, and C. Hu, “BSIM4v4.8.0 MOSFET
Model User’s Manual,” University of California, Berkeley, CA, 2013.
33. J.J. Paulous and D.A. Antoniadis, “Limitations of quasi-static capacitance models
for the MOS transistors,” IEEE Electron Device Letters, vol. 4, no. 7, pp. 221–224,
1983.
34. S.Y. Oh, D.E. Ward, and R.W. Dutton, “Transient analysis of MOS transistors,”
IEEE Journal of Solid-State Circuits, vol. 15, no. 4, pp. 636–643, 1980.
35. M. Chan, K.Y. Hui, C. Hui, and P.K. Ko, “A robust and physical BSIM3 nonquasi-static transient and AC small signal model for circuit simulation,” IEEE
Transactions on Electron Devices, vol. 45, no. 4, pp. 834–841, 1998.
36. P. Yang and P.K. Chatterjee, “SPICE modeling for small geometry MOSFET circuits,” IEEE Transactions on Computer-Aided Design, vol. 1, no. 4, pp. 169–182,
1982.
37. Y.P. Tsividis and G. Masetti, “Problems in the precision modeling of the MOS
transistor for analog applications,” IEEE Transactions on Computer-Aided Design,
vol. 3, no. 1, pp. 72–79, 1984.
38. T.L. Quarles, SPICE 3 Implementation Guide, Memorandum No. UCB/ERL
M89/44, April 1989.