492
References
48. S.-H. Lo, D.A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling
of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s,” IEEE Electron Device Letters, vol. 18, no. 5, pp. 209–211, 1997.
49. W.-C. Lee and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” in Symposium on VLSI
Technology, pp. 198–199, 2000.
50. N. Yang, W.K. Hension, J.R. Hauser, and J.J. Wortman, “Modeling study of
ultrathin gate oxides using direct tunneling current and CV measurements in
MOS devices,” IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1464–1471,
1999.
51. W.-C. Lee, and C. Hu, “Modeling CMOS tunneling currents through ultrathin
gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Transactions on Electron Devices, vol. 48, no. 7, pp. 1366–1373, July
2001.
52. J.B. Jacobs and D. Antoniadis, “Channel profile engineering for MOSFET’s with
100 nm channel lengths,” IEEE Transactions on Electron Devices, vol. 42, no. 5,
pp. 870–875, 1995.
53. S.A. Parke, J.E. Moon, H.C. Wann, P.K. Ko, and C. Hu, “Design for suppression
of gate-induced drain leakage in LDD MOSFET’s using a quasi-two dimensional analytical model,” IEEE Transactions on Electron Devices, vol. 39, no. 7,
pp. 1694–1703, 1992.
54. N. Lindert, M. Yoshida, C. Wann, and C. Hu, “Comparison of GIDL in p+-poly
PMOS and n+-poly PMOS devices,” IEEE Electron Device Letters, vol. 17, no. 6,
pp. 285–287, 1996.
55. T.Y. Chan, J. Chen, P.K. Ko, and C. Hu, “The impact of gate-induced drainleakage current on MOSFET scaling,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 718–721, 1987.
56. H.J. Wann, P.K. Ko, and C. Hu, “Gate-induced band-to-band tunneling leakage
current in LDD MOSFET’s,” in IEEE International Electron Devices Meeting Technical
Digest, pp. 147–150, 1992.
Chapter 6
1. Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor,
Oxford University Press, Oxford, 2011.
2. J. Meyer, “MOS models and circuit simulation,” RCA Review, vol. 32, no. 1,
pp. 42–63, 1971.
3. N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
4. D.E. Ward and R.W. Dutton, “A charge-oriented model for MOS transistor
capacitances,” IEEE Journal of Solid-State Circuits, vol. 13, no. 5, pp. 703–707,
1978.
5. S.Y. Oh, D.E. Ward, and R.W. Dutton, “Transient analysis of MOS transistors,”
IEEE Transactions on Electron Devices, vol. 27, no. 2, pp. 1571–1578, 1980.
References
48. S.-H. Lo, D.A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling
of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s,” IEEE Electron Device Letters, vol. 18, no. 5, pp. 209–211, 1997.
49. W.-C. Lee and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” in Symposium on VLSI
Technology, pp. 198–199, 2000.
50. N. Yang, W.K. Hension, J.R. Hauser, and J.J. Wortman, “Modeling study of
ultrathin gate oxides using direct tunneling current and CV measurements in
MOS devices,” IEEE Transactions on Electron Devices, vol. 46, no. 7, pp. 1464–1471,
1999.
51. W.-C. Lee, and C. Hu, “Modeling CMOS tunneling currents through ultrathin
gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Transactions on Electron Devices, vol. 48, no. 7, pp. 1366–1373, July
2001.
52. J.B. Jacobs and D. Antoniadis, “Channel profile engineering for MOSFET’s with
100 nm channel lengths,” IEEE Transactions on Electron Devices, vol. 42, no. 5,
pp. 870–875, 1995.
53. S.A. Parke, J.E. Moon, H.C. Wann, P.K. Ko, and C. Hu, “Design for suppression
of gate-induced drain leakage in LDD MOSFET’s using a quasi-two dimensional analytical model,” IEEE Transactions on Electron Devices, vol. 39, no. 7,
pp. 1694–1703, 1992.
54. N. Lindert, M. Yoshida, C. Wann, and C. Hu, “Comparison of GIDL in p+-poly
PMOS and n+-poly PMOS devices,” IEEE Electron Device Letters, vol. 17, no. 6,
pp. 285–287, 1996.
55. T.Y. Chan, J. Chen, P.K. Ko, and C. Hu, “The impact of gate-induced drainleakage current on MOSFET scaling,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 718–721, 1987.
56. H.J. Wann, P.K. Ko, and C. Hu, “Gate-induced band-to-band tunneling leakage
current in LDD MOSFET’s,” in IEEE International Electron Devices Meeting Technical
Digest, pp. 147–150, 1992.
Chapter 6
1. Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor,
Oxford University Press, Oxford, 2011.
2. J. Meyer, “MOS models and circuit simulation,” RCA Review, vol. 32, no. 1,
pp. 42–63, 1971.
3. N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
4. D.E. Ward and R.W. Dutton, “A charge-oriented model for MOS transistor
capacitances,” IEEE Journal of Solid-State Circuits, vol. 13, no. 5, pp. 703–707,
1978.
5. S.Y. Oh, D.E. Ward, and R.W. Dutton, “Transient analysis of MOS transistors,”
IEEE Transactions on Electron Devices, vol. 27, no. 2, pp. 1571–1578, 1980.