491
References
30. K.M. Cao, W. Liu, X. Jin, K. Vasanth, K. Green, J. Krick, T. Vrotsos, and C. Hu,
“Modeling of pocket implanted MOSFETs for anomalous analog behavior,” in
IEEE International Electron Devices Meeting Technical Digest, pp. 171–174, 1999.
31. S. Mudanai, W.-K. Shih, R. Rios, X. Xi, J.-H. Rhew, K. Kuhn, and P. Packan,
“Analytical modeling of output conductance in long-channel MOSFETs,” IEEE
Transactions on Electron Devices, vol. 53, no. 9, pp. 2091–2097, 2006.
32. G. Merckel, “A simple model of the threshold voltage of short and narrow channel MOSFETs,” Solid-State Electronics, vol. 23, no. 12, pp. 1207–1213, 1980.
33. L.D. Yau, “A simple theory to predict the threshold voltage of short-channel
IGFET’s,” Solid-State Electronics, vol. 17, no. 10, pp. 1059–1063, 1974.
34. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P.K. Ko, and Y.C. Cheng,
“Threshold voltage model for deep-submicron MOSFETs,” IEEE Transactions on
Electron Devices, vol. 40, no. 1, pp. 86–98, 1993.
35. N.D. Arora and G.Sh. Gildenblat, “A semi-empirical model of the MOSFET
inversion layer mobility for low temperature operation,” IEEE Transactions on
Electron Devices, vol. 34, no. 1, pp. 89–93, 1987.
36. S.C. Sun and J.D. Plummer, “Electron mobility in inversion and accumulation
layers on thermally grown oxidized silicon surfaces,” IEEE Transactions on
Electron Devices, vol. 27, no. 8, pp. 1497–1508, 1980.
37. D.T. Amm, H. Mingam, P. Delpech, and T.T. D’ouville, “Surface mobility in n+
and p+ doped polysilicon gate PMOS transistors,” IEEE Transactions on Electron
Devices, vol. 36, no. 5, pp. 963–968, 1989.
38. M.S. Liang, J.Y. Choi, P.-K. Ko, and C. Hu, “Inversion layer capacitance and
mobility of very thin oxide MOSFETs,” IEEE Transactions on Electron Devices,
vol. 33, no. 3, pp. 409–413, 1986.
39. K. Lee, J.Y. Choi, S.P. Sim, and C.K. Kim, “Physical understanding of low field
carrier mobility in silicon inversion layer,” IEEE Transactions on Electron Devices,
vol. 38, no. 8, pp. 1905–1912, 1991.
40. K. Chen, H.C. Wann, J. Dunster, P.K. Ko, and C. Hu, “MOSFET carrier mobility
model based on gate oxide thickness, threshold and gate voltages,” Solid-State
Electronics, vol. 39, no. 10, pp. 1515–1518, 1996.
41. Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Ko, and C. Hu,
“A physical and scalable BSIM3v3 I-V model for analog/digital circuit simulation,” IEEE Transactions on Electron Devices, vol. 44, no. 2, pp. 227–287, 1997.
42. S. Saha, C.S. Yeh, and B. Gadepally, “Impact ionization rate of electrons for
accurate simulation of substrate current in submicron devices,” Solid-State
Electronics, vol. 36, no. 10, pp. 1429–1432, 1993.
43. S. Saha, “Hot-carrier reliability in sub-0.1 μm nMOSFET devices,” in Materials
Research Society Symposia Proceedings, vol. 428, p. 379–384, 1996.
44. J.W. Slotboom, G. Streutker, G.J.T. Davids, and P.B. Hartong, “Surface impact
ionization in silicon devices,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 494–497, 1987.
45. N.D. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
46. T.Y. Chan, P.K. Ko, and C. Hu, “A simple method to characterize substrate current in MOSFET’s,” IEEE Electron Device Letters, vol. 5, no. 12, pp. 505–507, 1984.
47. S. Saha, “Extraction of substrate current model parameters from device
simulation,”Solid-State Electronics, vol. 37, no. 10, pp. 1786–1788, 1994.
References
30. K.M. Cao, W. Liu, X. Jin, K. Vasanth, K. Green, J. Krick, T. Vrotsos, and C. Hu,
“Modeling of pocket implanted MOSFETs for anomalous analog behavior,” in
IEEE International Electron Devices Meeting Technical Digest, pp. 171–174, 1999.
31. S. Mudanai, W.-K. Shih, R. Rios, X. Xi, J.-H. Rhew, K. Kuhn, and P. Packan,
“Analytical modeling of output conductance in long-channel MOSFETs,” IEEE
Transactions on Electron Devices, vol. 53, no. 9, pp. 2091–2097, 2006.
32. G. Merckel, “A simple model of the threshold voltage of short and narrow channel MOSFETs,” Solid-State Electronics, vol. 23, no. 12, pp. 1207–1213, 1980.
33. L.D. Yau, “A simple theory to predict the threshold voltage of short-channel
IGFET’s,” Solid-State Electronics, vol. 17, no. 10, pp. 1059–1063, 1974.
34. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P.K. Ko, and Y.C. Cheng,
“Threshold voltage model for deep-submicron MOSFETs,” IEEE Transactions on
Electron Devices, vol. 40, no. 1, pp. 86–98, 1993.
35. N.D. Arora and G.Sh. Gildenblat, “A semi-empirical model of the MOSFET
inversion layer mobility for low temperature operation,” IEEE Transactions on
Electron Devices, vol. 34, no. 1, pp. 89–93, 1987.
36. S.C. Sun and J.D. Plummer, “Electron mobility in inversion and accumulation
layers on thermally grown oxidized silicon surfaces,” IEEE Transactions on
Electron Devices, vol. 27, no. 8, pp. 1497–1508, 1980.
37. D.T. Amm, H. Mingam, P. Delpech, and T.T. D’ouville, “Surface mobility in n+
and p+ doped polysilicon gate PMOS transistors,” IEEE Transactions on Electron
Devices, vol. 36, no. 5, pp. 963–968, 1989.
38. M.S. Liang, J.Y. Choi, P.-K. Ko, and C. Hu, “Inversion layer capacitance and
mobility of very thin oxide MOSFETs,” IEEE Transactions on Electron Devices,
vol. 33, no. 3, pp. 409–413, 1986.
39. K. Lee, J.Y. Choi, S.P. Sim, and C.K. Kim, “Physical understanding of low field
carrier mobility in silicon inversion layer,” IEEE Transactions on Electron Devices,
vol. 38, no. 8, pp. 1905–1912, 1991.
40. K. Chen, H.C. Wann, J. Dunster, P.K. Ko, and C. Hu, “MOSFET carrier mobility
model based on gate oxide thickness, threshold and gate voltages,” Solid-State
Electronics, vol. 39, no. 10, pp. 1515–1518, 1996.
41. Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Ko, and C. Hu,
“A physical and scalable BSIM3v3 I-V model for analog/digital circuit simulation,” IEEE Transactions on Electron Devices, vol. 44, no. 2, pp. 227–287, 1997.
42. S. Saha, C.S. Yeh, and B. Gadepally, “Impact ionization rate of electrons for
accurate simulation of substrate current in submicron devices,” Solid-State
Electronics, vol. 36, no. 10, pp. 1429–1432, 1993.
43. S. Saha, “Hot-carrier reliability in sub-0.1 μm nMOSFET devices,” in Materials
Research Society Symposia Proceedings, vol. 428, p. 379–384, 1996.
44. J.W. Slotboom, G. Streutker, G.J.T. Davids, and P.B. Hartong, “Surface impact
ionization in silicon devices,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 494–497, 1987.
45. N.D. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
46. T.Y. Chan, P.K. Ko, and C. Hu, “A simple method to characterize substrate current in MOSFET’s,” IEEE Electron Device Letters, vol. 5, no. 12, pp. 505–507, 1984.
47. S. Saha, “Extraction of substrate current model parameters from device
simulation,”Solid-State Electronics, vol. 37, no. 10, pp. 1786–1788, 1994.