490
References
12. M.S. Liang, J.Y. Choi, P.-K. Ko, and C. Hu, “Inversion layer capacitance and
mobility of very thin oxide MOSFETs,” IEEE Transactions on Electron Devices,
vol. 33, no. 3, pp. 409–413, 1986.
13. C. Hu, “Hot Carrier Effects,” in Advanced MOS Device and Physics, N.G.
Einspruch, and G. Gildenblat, eds., vol. 18, VLSI Electronics Microstructure
Science, Academic Press, New York, vol. 18, pp. 119–139, 1989.
14. I.C. Chen, C.W. Teng, D.J. Coleman, and A. Nishimura, “Interface-trap enhanced
gate-induced leakage current in MOSFET,” IEEE Electron Device Letters, vol. 10,
no. 5, pp. 216–218, 1989.
15. F. Assderaghi, P.K. Ko, and C. Hu, “Observation of velocity overshoot in silicon
in version layers,” IEEE Electron Device Letters, vol. 14, no. 10, p. 484–486, 1993.
16. Y. Cheng and T.A. Fjeldly, “Unified physical I–V model including self-heating
effect for fully depleted SOI/MOSFET’s,” IEEE Transactions on Electron Devices,
vol. 43, no. 8, pp. 1291–1296, 1996.
17. Y.-C. King, H. Fujioka, S. Kamohara, W.C. Lee, and C. Hu, “AC charge centroid model for quantization of inversion layer in NMOSFET,” in International
Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical
Papers, Taipei, Taiwan, pp. 245–249, June 1997.
18. M.J. van Dort, P.H. Woerlee, and A.J. Walker, “A simple model for quantisation
effects in heavily-doped silicon MOSFETs at inversion conditions,” Solid-State
Electronics, vol. 37, no. 3, pp. 411–414, 1994.
19. S. Saha, “Effects of inversion layer quantization on channel profile engineering
for nMOSFETs with 0.1 μm channel lengths,” Solid-State Electronics, vol. 42,
no. 11, pp. 1985–1991, 1998.
20. K. Chen et al., “Polysilicon gate depletion effect on IC performance,” Solid-State
Electronics, vol. 38, no. 11, pp. 1975–1977, 1995.
21. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
22. S.K. Saha, “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 104–115, 2014.
23. S.K. Saha, “Method for forming channel-region doping profile for semiconductor device,” US Patent 6,323,520, November 27, 2001.
24. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6,344,405, February 5, 2002.
25. S.K. Saha, “Drain profile engineering for MOSFET devices with channel
lengths below 100 nm,” Proceedings of the SPIE Conference on Microelectronic
Device Technology, vol. 3881, pp. 195–204, 1999.
26. S. Saha, “Device characteristics of sub-20-nm silicon nanotransistors,” Proceedings of the SPIE Conference on Design and Process Integration for Microelectronic
Manu facturing, vol. 5042, pp. 172–179, 2003.
27. J.H. Huang, Z.H. Liu, M.C. Jeng, P. Ko, and C. Hu, “A physical model for
MOSFET output resistance,” International Electron Devices Meeting. Technical
Digest, pp. 569–572, IEEE, 1992.
28. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He et al.,
BSIM4v4.8.0 MOSFET Model User’s Manual, University of California, Berkeley,
CA, 2013.
29. Y. Cheng and C. Hu, MOSFET modeling and BSIM3 user’s Guide, Kluwer
Academic Publishers, Boston, MA, 1999.
References
12. M.S. Liang, J.Y. Choi, P.-K. Ko, and C. Hu, “Inversion layer capacitance and
mobility of very thin oxide MOSFETs,” IEEE Transactions on Electron Devices,
vol. 33, no. 3, pp. 409–413, 1986.
13. C. Hu, “Hot Carrier Effects,” in Advanced MOS Device and Physics, N.G.
Einspruch, and G. Gildenblat, eds., vol. 18, VLSI Electronics Microstructure
Science, Academic Press, New York, vol. 18, pp. 119–139, 1989.
14. I.C. Chen, C.W. Teng, D.J. Coleman, and A. Nishimura, “Interface-trap enhanced
gate-induced leakage current in MOSFET,” IEEE Electron Device Letters, vol. 10,
no. 5, pp. 216–218, 1989.
15. F. Assderaghi, P.K. Ko, and C. Hu, “Observation of velocity overshoot in silicon
in version layers,” IEEE Electron Device Letters, vol. 14, no. 10, p. 484–486, 1993.
16. Y. Cheng and T.A. Fjeldly, “Unified physical I–V model including self-heating
effect for fully depleted SOI/MOSFET’s,” IEEE Transactions on Electron Devices,
vol. 43, no. 8, pp. 1291–1296, 1996.
17. Y.-C. King, H. Fujioka, S. Kamohara, W.C. Lee, and C. Hu, “AC charge centroid model for quantization of inversion layer in NMOSFET,” in International
Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical
Papers, Taipei, Taiwan, pp. 245–249, June 1997.
18. M.J. van Dort, P.H. Woerlee, and A.J. Walker, “A simple model for quantisation
effects in heavily-doped silicon MOSFETs at inversion conditions,” Solid-State
Electronics, vol. 37, no. 3, pp. 411–414, 1994.
19. S. Saha, “Effects of inversion layer quantization on channel profile engineering
for nMOSFETs with 0.1 μm channel lengths,” Solid-State Electronics, vol. 42,
no. 11, pp. 1985–1991, 1998.
20. K. Chen et al., “Polysilicon gate depletion effect on IC performance,” Solid-State
Electronics, vol. 38, no. 11, pp. 1975–1977, 1995.
21. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
22. S.K. Saha, “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 104–115, 2014.
23. S.K. Saha, “Method for forming channel-region doping profile for semiconductor device,” US Patent 6,323,520, November 27, 2001.
24. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6,344,405, February 5, 2002.
25. S.K. Saha, “Drain profile engineering for MOSFET devices with channel
lengths below 100 nm,” Proceedings of the SPIE Conference on Microelectronic
Device Technology, vol. 3881, pp. 195–204, 1999.
26. S. Saha, “Device characteristics of sub-20-nm silicon nanotransistors,” Proceedings of the SPIE Conference on Design and Process Integration for Microelectronic
Manu facturing, vol. 5042, pp. 172–179, 2003.
27. J.H. Huang, Z.H. Liu, M.C. Jeng, P. Ko, and C. Hu, “A physical model for
MOSFET output resistance,” International Electron Devices Meeting. Technical
Digest, pp. 569–572, IEEE, 1992.
28. N. Paydavosi, T.H. Morshed, D.D. Lu, W. Yang, M.V. Dunga, X. Xi, J. He et al.,
BSIM4v4.8.0 MOSFET Model User’s Manual, University of California, Berkeley,
CA, 2013.
29. Y. Cheng and C. Hu, MOSFET modeling and BSIM3 user’s Guide, Kluwer
Academic Publishers, Boston, MA, 1999.