489
References
27. C.T. Sah, “Characteristics of the metal-oxide-semiconductor transistors,” IEEE
Transactions on Electron Devices, vol. 11, no. 7, pp. 324–345, 1964.
28. H. Shichman and D.A. Hodges, “Modeling and simulation of insulated-gate
field-effect transistor switching circuits,” IEEE Journal Solid-State Circuits, vol. 3,
no. 3, pp. 285–289, 1968.
29. H.K.J. Ihantola and J.L. Moll, “Design theory of a surface field-effect transistor,”
Solid-State Electronics, vol. 7, no. 6, pp. 423–430, 1964.
30. B.J. Sheu, D.L. Scharfetter, P.K. Ko, and M.C. Jeng, “BSIM: Berkeley short-channel
IGFET models for MOS transistors,” IEEE Journal on Solid-State Circuits, vol. 22,
no. 4, pp. 558–565, 1987.
31. G.T. Wright, “Physical and CAD model for the implanted-channel VLSI
MOSFET,” IEEE Transactions on Electron Devices, vol. 34, no. 4, pp. 823–833, 1987.
32. R.M. Swanson and J.D. Meindel, “Ion implanted complementary MOS transistors in low-voltage circuits,” IEEE Journal on Solid-State Circuits, vol. 7, no. 2,
pp. 146–143, 1972.
Chapter 5
1. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
2. H. Iwai, “CMOS technology—Year 2010 and beyond,” IEEE Journal of Solid-State
Circuits, vol. 34, no. 3, pp. 357–366, 1999.
3. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
4. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
5. C. Duvvury, “A guide to short channel effects in MOSFETS,” IEEE Circuit and
Systems Magazine, vol. 2, no.6, pp. 6–10, 1986.
6. C.Y. Lu and J.M. Sung, “Reverse short channel effects on threshold voltage in
submicron salicide devices,” IEEE Electron Device Letters, vol. l0, p. 446, 1989.
7. E.H. Li et al., “The narrow channel effect in MOSFET with semi-recessed
oxide structures,” IEEE Transactions on Electron Devices, vol. 37, no. 3, p. 692,
1990.
8. L.A. Akers, “The inverse narrow width effect,” IEEE Electron Device Letters, vol. 7,
no. 7, p. 419, 1986.
9. W. Fichtner and H.W. Potzl, “MOS modeling by analytical approximationssubthreshold current and subthreshold voltage,” International Journal of Electronics, vol. 46, no. 1, pp. 33–35, 1979.
10. R.R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE
Transactions on Electron Devices, vol. 26, no, 4, pp. 461–469, 1979.
11. C.G. Sodini, P.K. Ko, and J.L. Moll, “The effect of high fields on MOS device and circuit simulation,” IEEE Transactions on Electron Devices, vol. 31, no. 10, pp. 1386–1393,
October 1984.
References
27. C.T. Sah, “Characteristics of the metal-oxide-semiconductor transistors,” IEEE
Transactions on Electron Devices, vol. 11, no. 7, pp. 324–345, 1964.
28. H. Shichman and D.A. Hodges, “Modeling and simulation of insulated-gate
field-effect transistor switching circuits,” IEEE Journal Solid-State Circuits, vol. 3,
no. 3, pp. 285–289, 1968.
29. H.K.J. Ihantola and J.L. Moll, “Design theory of a surface field-effect transistor,”
Solid-State Electronics, vol. 7, no. 6, pp. 423–430, 1964.
30. B.J. Sheu, D.L. Scharfetter, P.K. Ko, and M.C. Jeng, “BSIM: Berkeley short-channel
IGFET models for MOS transistors,” IEEE Journal on Solid-State Circuits, vol. 22,
no. 4, pp. 558–565, 1987.
31. G.T. Wright, “Physical and CAD model for the implanted-channel VLSI
MOSFET,” IEEE Transactions on Electron Devices, vol. 34, no. 4, pp. 823–833, 1987.
32. R.M. Swanson and J.D. Meindel, “Ion implanted complementary MOS transistors in low-voltage circuits,” IEEE Journal on Solid-State Circuits, vol. 7, no. 2,
pp. 146–143, 1972.
Chapter 5
1. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
2. H. Iwai, “CMOS technology—Year 2010 and beyond,” IEEE Journal of Solid-State
Circuits, vol. 34, no. 3, pp. 357–366, 1999.
3. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
4. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
5. C. Duvvury, “A guide to short channel effects in MOSFETS,” IEEE Circuit and
Systems Magazine, vol. 2, no.6, pp. 6–10, 1986.
6. C.Y. Lu and J.M. Sung, “Reverse short channel effects on threshold voltage in
submicron salicide devices,” IEEE Electron Device Letters, vol. l0, p. 446, 1989.
7. E.H. Li et al., “The narrow channel effect in MOSFET with semi-recessed
oxide structures,” IEEE Transactions on Electron Devices, vol. 37, no. 3, p. 692,
1990.
8. L.A. Akers, “The inverse narrow width effect,” IEEE Electron Device Letters, vol. 7,
no. 7, p. 419, 1986.
9. W. Fichtner and H.W. Potzl, “MOS modeling by analytical approximationssubthreshold current and subthreshold voltage,” International Journal of Electronics, vol. 46, no. 1, pp. 33–35, 1979.
10. R.R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE
Transactions on Electron Devices, vol. 26, no, 4, pp. 461–469, 1979.
11. C.G. Sodini, P.K. Ko, and J.L. Moll, “The effect of high fields on MOS device and circuit simulation,” IEEE Transactions on Electron Devices, vol. 31, no. 10, pp. 1386–1393,
October 1984.