487
References
9. T. Kamins, Polycrystalline Silicon for IC Application, 2nd edition, Kluwer Academic
Publisher, Boston, MA, 1998.
10. B.E. Deal, “Standardized terminology for oxide charge associated with thermally oxidized silicon,” IEEE Transactions on Electronic Devices, vol. 27, no. 3,
pp. 606–608, 1980.
11. D.K. Schroder, Semiconductor Materials and Device Characterization, John Wiley &
Sons, New York, 1990.
12. B.G. Streetman and S. Banerjee, Solid State Electronic Devices, 7th edition,
Prentice Hall, Englewood Cliffs, NJ, 2014.
13. M.J. van Dort, P.H. Woerlee, and A.J. Walker, “A simple model for quantisation
effects in heavily-doped silicon MOSFETs at inversion conditions,” Solid-State
Electronics, vol. 37, no. 3, pp. 411–414, 1994.
14. R.A. Chapman, C.C. Wei, D.A. Bell, S. Aur, G.A. Brown, and R.A. Haken, “0.5
micron CMOS for high performance at 3.3 V,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 52–55, 1988.
15. C.Y. Wong, J.Y.-C. Sun, Y.T. Aur, C.S. Oh, R. Angelucci, and B. Davari, “Doping of
N+ and P+ poly_si in a dual-gate CMOS process,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 238–241, 1988.
16. C.Y. Lu, J.M. Sung, H.C. Kirch, S.J. Hellenius, T.E. Smith, and L. Manchanda,
“Anomalous C-V characteristics of implanted poly MOS structure in n+/p+ dualgate CMOS technology,” IEEE Electron Device Letters, vol. 10, no. 5, pp.192–194, 1989.
17. P. Habas and S. Selberherr, “On the effect of nondegenerate doping of polysilicon
gate in thin oxide MOS devices–analytical modeling,” Solid-State Electronics,
vol. 33, no. 12, pp. 1539–1544, 1990.
18. S. Saha, G. Srinivasan, G.A. Rezvani, and M. Farr, “Effects of inversion layer
quantization and polysilicon gate depletion on tunneling current of ultra-thin
SiO 2 gate material,” Materials Research Society Symposium Proceedings, vol. 567,
pp. 275–282, 1999.
19. G. Srinivasan, S.K. Saha, and G.A. Rezvani, “Estimation of quantum mechanical and polysilicon depletion effects for ultra-thin SiO 2 gate dielectric,” in
Proceedings of the SPIE Conference on Microelectronic Device Technology, vol. 3881,
pp. 168–174, 1999.
Chapter 4
1. J.E. Lilenfield, “Methods and apparatus for controlling electric currents,” US
Patent 1745175, January 28, 1930.
2. H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9, no. 10,
pp. 927–937, 1966.
3. R.F. Pierret and J.A. Shields, “Simplified long-channel MOSFET theory,” SolidState Electronics, vol. 26, no. 2, pp. 143–147, 1983.
4. A. Naussbaum, R. Sinha, and D. Dokos, “The theory of the long-channel
MOSFET,” Solid-State Electronics, vol. 27, no. 1, pp. 97–106, 1984.
References
9. T. Kamins, Polycrystalline Silicon for IC Application, 2nd edition, Kluwer Academic
Publisher, Boston, MA, 1998.
10. B.E. Deal, “Standardized terminology for oxide charge associated with thermally oxidized silicon,” IEEE Transactions on Electronic Devices, vol. 27, no. 3,
pp. 606–608, 1980.
11. D.K. Schroder, Semiconductor Materials and Device Characterization, John Wiley &
Sons, New York, 1990.
12. B.G. Streetman and S. Banerjee, Solid State Electronic Devices, 7th edition,
Prentice Hall, Englewood Cliffs, NJ, 2014.
13. M.J. van Dort, P.H. Woerlee, and A.J. Walker, “A simple model for quantisation
effects in heavily-doped silicon MOSFETs at inversion conditions,” Solid-State
Electronics, vol. 37, no. 3, pp. 411–414, 1994.
14. R.A. Chapman, C.C. Wei, D.A. Bell, S. Aur, G.A. Brown, and R.A. Haken, “0.5
micron CMOS for high performance at 3.3 V,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 52–55, 1988.
15. C.Y. Wong, J.Y.-C. Sun, Y.T. Aur, C.S. Oh, R. Angelucci, and B. Davari, “Doping of
N+ and P+ poly_si in a dual-gate CMOS process,” in IEEE International Electron
Devices Meeting Technical Digest, pp. 238–241, 1988.
16. C.Y. Lu, J.M. Sung, H.C. Kirch, S.J. Hellenius, T.E. Smith, and L. Manchanda,
“Anomalous C-V characteristics of implanted poly MOS structure in n+/p+ dualgate CMOS technology,” IEEE Electron Device Letters, vol. 10, no. 5, pp.192–194, 1989.
17. P. Habas and S. Selberherr, “On the effect of nondegenerate doping of polysilicon
gate in thin oxide MOS devices–analytical modeling,” Solid-State Electronics,
vol. 33, no. 12, pp. 1539–1544, 1990.
18. S. Saha, G. Srinivasan, G.A. Rezvani, and M. Farr, “Effects of inversion layer
quantization and polysilicon gate depletion on tunneling current of ultra-thin
SiO 2 gate material,” Materials Research Society Symposium Proceedings, vol. 567,
pp. 275–282, 1999.
19. G. Srinivasan, S.K. Saha, and G.A. Rezvani, “Estimation of quantum mechanical and polysilicon depletion effects for ultra-thin SiO 2 gate dielectric,” in
Proceedings of the SPIE Conference on Microelectronic Device Technology, vol. 3881,
pp. 168–174, 1999.
Chapter 4
1. J.E. Lilenfield, “Methods and apparatus for controlling electric currents,” US
Patent 1745175, January 28, 1930.
2. H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9, no. 10,
pp. 927–937, 1966.
3. R.F. Pierret and J.A. Shields, “Simplified long-channel MOSFET theory,” SolidState Electronics, vol. 26, no. 2, pp. 143–147, 1983.
4. A. Naussbaum, R. Sinha, and D. Dokos, “The theory of the long-channel
MOSFET,” Solid-State Electronics, vol. 27, no. 1, pp. 97–106, 1984.