483
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A.G. Andreou (eds.). pp. 7–55, IEEE Press, New York, 1999.
110. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure,” Solid-State
Electronics, vol. 43, no. 3, pp. 481–485, 1999.
111. O.C. Gouveia Filho, A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro,
“Advanced compact model for short-channel MOS transistors,” Proceedings of the
IEEE Custom Integrated Circuits Conference, pp. 209–212, IEEE, 2000.
112. A. Arnaud and C. Galup-Montoro, “A compact model for flicker noise in MOS
transistors for analog circuit design,” IEEE Transactions on Electron Devices,
vol. 50, no. 9, pp. 1815–1818, 2003.
113. C. Galup-Montoro, M.C. Schneider, A. Arnaud, and H. Klimach, “Self-consistent
models of DC, AC, noise and mismatch for the MOSFET,” Proceedings of the
Nanotech Workshop on Compact Modeling, vol. 2, pp. 494–499, 2004.
114. E. Vittoz, and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,” IEEE Journal of Solid-State Circuits, vol. 12, no. 3, pp. 224–231, 1977.
115. J.D. Chatelaine, Dispositifs a Semiconducteur, vol. 7, 1st edition, Dunod, Paris,
France, 1979.
116. A.I.A. Cunha, O.C. Gouveia-Filho, M.C. Schneider, and C. Galup-Montoro, “A current based model for the MOS transistor,” IEEE International Symposium on Circuits
and Systems, vol. 3, pp. 1608–1611, 1997.
117. M. Bucher, C. Lallement, C. Enz, F. Théodoloz, F. Krummenacher, “Scalable
GM/I based MOSFET model,” in International Semiconductor Device Research
Symposium, pp. 615–618, 1997.
118. J.-M. Sallese and A.-S. Porret, “A novel approach to charge-based non-quasistatic
model of the MOS transistor valid in all modes of operation,” Solid-State Electronics,
vol. 44, no. 6, pp. 887–894, 2000.
119. C. Lallement, J.-M. Sallese, M. Bucher, W. Grabinski, and P. Fazan, “Accounting
for quantum effects and polysilicon depletion from weak to strong inversion in
References
103. H.K. Gummel and K. Singhal, “Inversion charge modeling,” IEEE Transactions
on Electron Devices, vol. 48, no. 8, pp. 1585–1593, 2001.
104. J. He, X. Xi, M. Chan, A. Niknejad, and C. Hu, “An advanced surface-potentialplus MOSFET model,” in Technical Proceedings, Workshop on Compact Modeling,
NSTI Nanotech, pp. 307–310, 2005.
105. C. Galup-Montoro, M.C. Schneider, and I.J.B. Loss, “Series-parallel association
of FET’s for high gain and high frequency applications,” IEEE Journal of SolidState Circuits, vol. 29, no. 9, pp. 1094–1101, 1994.
106. O.C. Gouveia Filho, A.I.A. Cunha, M.C. Schneider, and C.G. Montoro, “The
ACM model for circuit simulation and equations for smash,” September 1997.
http://www.dolphin.fr/medal/downloads/notes/acm_report.pdf, accessed
May 26, 2015.
107. A.T. Behr, M.C. Schneider, F.S. Noceti, and C.G. Montoro, “Nonlinearities of
capacitors realized by MOSFET gates,” in Proceedings of the IEEE International
Conference on Circuits and Systems (ISCAS’92), pp. 1284–1287, 1992.
108. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, “An MOS transistor
model for analog circuit design,” IEEE Journal of Solid-State Circuits, vol. 33,
no. 10, pp. 1510–1519, 1998.
109. C. Galup-Montoro, M.C. Schneider, and A.I.A. Cunha, “Current-based MOSFET
model for integrated circuit design,” in Low-Voltage/Low-Power Integrated
Circuits and Systems: Low Voltage Mixed-Signal Circuits, E. Sanchez-Sinencio, and
A.G. Andreou (eds.). pp. 7–55, IEEE Press, New York, 1999.
110. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, “Derivation of the unified charge control model and parameter extraction procedure,” Solid-State
Electronics, vol. 43, no. 3, pp. 481–485, 1999.
111. O.C. Gouveia Filho, A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro,
“Advanced compact model for short-channel MOS transistors,” Proceedings of the
IEEE Custom Integrated Circuits Conference, pp. 209–212, IEEE, 2000.
112. A. Arnaud and C. Galup-Montoro, “A compact model for flicker noise in MOS
transistors for analog circuit design,” IEEE Transactions on Electron Devices,
vol. 50, no. 9, pp. 1815–1818, 2003.
113. C. Galup-Montoro, M.C. Schneider, A. Arnaud, and H. Klimach, “Self-consistent
models of DC, AC, noise and mismatch for the MOSFET,” Proceedings of the
Nanotech Workshop on Compact Modeling, vol. 2, pp. 494–499, 2004.
114. E. Vittoz, and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,” IEEE Journal of Solid-State Circuits, vol. 12, no. 3, pp. 224–231, 1977.
115. J.D. Chatelaine, Dispositifs a Semiconducteur, vol. 7, 1st edition, Dunod, Paris,
France, 1979.
116. A.I.A. Cunha, O.C. Gouveia-Filho, M.C. Schneider, and C. Galup-Montoro, “A current based model for the MOS transistor,” IEEE International Symposium on Circuits
and Systems, vol. 3, pp. 1608–1611, 1997.
117. M. Bucher, C. Lallement, C. Enz, F. Théodoloz, F. Krummenacher, “Scalable
GM/I based MOSFET model,” in International Semiconductor Device Research
Symposium, pp. 615–618, 1997.
118. J.-M. Sallese and A.-S. Porret, “A novel approach to charge-based non-quasistatic
model of the MOS transistor valid in all modes of operation,” Solid-State Electronics,
vol. 44, no. 6, pp. 887–894, 2000.
119. C. Lallement, J.-M. Sallese, M. Bucher, W. Grabinski, and P. Fazan, “Accounting
for quantum effects and polysilicon depletion from weak to strong inversion in