481
References
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on Compact Modeling, NSTI Nanotech, pp. 3–11, 2005.
71. M. Miura-Mattausch et al., “HiSIM2: An advanced MOSFET model valid for
RF circuit simulation,” IEEE Transactions on Electron Devices, vol. 53, no. 9,
pp. 1994–2007, 2006.
72. R. van Langevelde, A.J. Scholten, and D.B.M. Klaassen, “Physical background of MOS11,” Level 1101 Nat. Lab. Unclassified Report 2003/00239,
Koninklijke Philips Electronics, Amsterdam, the Netherlands, April 2003.
http://www.nxp.com/wcm_documents/models/mos-models/model-11/
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73. R. van Langevelde, J. Paasschens, A. Scholten, R. Havens, L. Tiemeijer, and
D. Klaassen, “New compact model for induced gate current noise,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 867–870, 2003.
74. R. van Langevelde, A.J. Scholten, R. Duffy, F.N. Cubaynes, M.J. Knitel, and
D.B.M. Klaassen, “Gate current: Modeling, ∆L extraction and impact on RF performance,” in IEEE International Electron Devices Meeting Technical Digest, 2001,
pp. 289–292.
75. R. van Langevelde and F.M. Klaassen, “Effect of gate-field dependent mobility
degradation on distortion analysis in MOSFETs,” IEEE Transactions on Electron
Devices, vol. 44, no. 11, pp. 2044–2052, 1997.
76. R. van Langevelde and F.M. Klaassen, “Accurate drain conductance modeling for distortion analysis in MOSFETs,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 313–316, 1997.
77. R. van Langevelde, L. Tiemeijer, R. Havens, M. Knitel, R. Roes, P. Woerlee, and
D. Klaassen, “RF-distortion in deep-submicron CMOS technologies,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 807–810, 2000.
78. D.B.M. Klaassen, R.V. Langevelde, and A.J. Scholten, “Compact CMOS modeling
for advanced analogue and RF applications,” IEICE Transactions on Electronics,
vol. E87-C, no. 6, pp. 854–866, 2004.
79. K. Joardar, K.K. Gullapalli, C.C. McAndrew, M.E. Burnham, and A. Wild,
“An improved MOSFET model for circuit simulation,” IEEE Transactions on Electron
Devices, vol. 45, no. 1, pp. 134–148, 1998.
80. R. van Langevelde, A.J. Scholten, R.J. Havens, L.F. Tiemeijer, and D.B.M.
Klaassen, “Advanced compact MOS modelling,” in Proceedings of the
European Solid-State Device Research Conference, pp. 81–88, 2001.
81. A.J. Scholten, R. Duffy, R. van Langevelde, and D.B.M. Klaassen, “Compact
MOS modelling of pocket-implanted MOSFETs,” in Proceedings of the European
Solid-State Device Research Conference, pp. 311–314, 2001.
82. R. van Langevelde and F.M. Klaassen, “An explicit surface-potential based
MOSFET model for circuit simulation,” Solid-State Electronics, vol. 44, no. 11,
pp. 409–418, 2000.
83. M. Miura-Mattausch and U. Weinert, “Unified MOSFET model for all channel
lengths down to quarter micron,” IEICE Transactions on Electronics, vol. E75-C,
no. 2, pp. 172–180, 1992.
84. C.-L. Huang and G.S. Gildenblat, “Correction factor in the split C–V method for
mobility measurements,” Solid-State Electronics, vol. 36, no, 4, pp. 611–615, 1993.
85. G. Gildenblat, H. Wang, T.-L. Chen, X. Gu, and X. Cai, “SP: An advanced
surface-potential-based compact MOSFET model,” IEEE Journal of Solid-State
Circuits, vol. 39, no. 9, pp. 1394–1406, 2004.
References
compact models for MOSFETs,” in Technical Proceedings, International Workshop
on Compact Modeling, NSTI Nanotech, pp. 3–11, 2005.
71. M. Miura-Mattausch et al., “HiSIM2: An advanced MOSFET model valid for
RF circuit simulation,” IEEE Transactions on Electron Devices, vol. 53, no. 9,
pp. 1994–2007, 2006.
72. R. van Langevelde, A.J. Scholten, and D.B.M. Klaassen, “Physical background of MOS11,” Level 1101 Nat. Lab. Unclassified Report 2003/00239,
Koninklijke Philips Electronics, Amsterdam, the Netherlands, April 2003.
http://www.nxp.com/wcm_documents/models/mos-models/model-11/
nl_tn2003_00239.pdf, accessed May 26, 2015.
73. R. van Langevelde, J. Paasschens, A. Scholten, R. Havens, L. Tiemeijer, and
D. Klaassen, “New compact model for induced gate current noise,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 867–870, 2003.
74. R. van Langevelde, A.J. Scholten, R. Duffy, F.N. Cubaynes, M.J. Knitel, and
D.B.M. Klaassen, “Gate current: Modeling, ∆L extraction and impact on RF performance,” in IEEE International Electron Devices Meeting Technical Digest, 2001,
pp. 289–292.
75. R. van Langevelde and F.M. Klaassen, “Effect of gate-field dependent mobility
degradation on distortion analysis in MOSFETs,” IEEE Transactions on Electron
Devices, vol. 44, no. 11, pp. 2044–2052, 1997.
76. R. van Langevelde and F.M. Klaassen, “Accurate drain conductance modeling for distortion analysis in MOSFETs,” in IEEE International Electron Devices
Meeting Technical Digest, pp. 313–316, 1997.
77. R. van Langevelde, L. Tiemeijer, R. Havens, M. Knitel, R. Roes, P. Woerlee, and
D. Klaassen, “RF-distortion in deep-submicron CMOS technologies,” in IEEE
International Electron Devices Meeting Technical Digest, pp. 807–810, 2000.
78. D.B.M. Klaassen, R.V. Langevelde, and A.J. Scholten, “Compact CMOS modeling
for advanced analogue and RF applications,” IEICE Transactions on Electronics,
vol. E87-C, no. 6, pp. 854–866, 2004.
79. K. Joardar, K.K. Gullapalli, C.C. McAndrew, M.E. Burnham, and A. Wild,
“An improved MOSFET model for circuit simulation,” IEEE Transactions on Electron
Devices, vol. 45, no. 1, pp. 134–148, 1998.
80. R. van Langevelde, A.J. Scholten, R.J. Havens, L.F. Tiemeijer, and D.B.M.
Klaassen, “Advanced compact MOS modelling,” in Proceedings of the
European Solid-State Device Research Conference, pp. 81–88, 2001.
81. A.J. Scholten, R. Duffy, R. van Langevelde, and D.B.M. Klaassen, “Compact
MOS modelling of pocket-implanted MOSFETs,” in Proceedings of the European
Solid-State Device Research Conference, pp. 311–314, 2001.
82. R. van Langevelde and F.M. Klaassen, “An explicit surface-potential based
MOSFET model for circuit simulation,” Solid-State Electronics, vol. 44, no. 11,
pp. 409–418, 2000.
83. M. Miura-Mattausch and U. Weinert, “Unified MOSFET model for all channel
lengths down to quarter micron,” IEICE Transactions on Electronics, vol. E75-C,
no. 2, pp. 172–180, 1992.
84. C.-L. Huang and G.S. Gildenblat, “Correction factor in the split C–V method for
mobility measurements,” Solid-State Electronics, vol. 36, no, 4, pp. 611–615, 1993.
85. G. Gildenblat, H. Wang, T.-L. Chen, X. Gu, and X. Cai, “SP: An advanced
surface-potential-based compact MOSFET model,” IEEE Journal of Solid-State
Circuits, vol. 39, no. 9, pp. 1394–1406, 2004.