479
References
34. H. Schichmann and D. Hodges, “Modeling and simulation of insulated-gate
field-effect transistor switching circuits,” IEEE Journal of Solid-State Circuits,
vol. 3, no. 3, pp. 285–289, 1968.
35. A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits
using SPICE2,” University of California, Berkeley, CA, Electronics Research
Laboratory Memorandum No. UCB/ERL M80/7, 1980.
36. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R.
LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256–268, 1974.
37. F. van de Wiele, “A long channel MOSFET model,” Solid-State Electronics, vol. 22,
no. 12, pp. 991–997, 1979.
38. C.C. McAndrew and J.J. Victory, “Accuracy of approximations in MOSFET charge
models,” IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 72–81, 2002.
39. S. Liu, “A unified CAD model for MOSFETs,” University of California, Berkeley,
CA, Electronics Research Laboratory Memorandum No. UCB/ERL M81/31, 1981.
40. M.C. Jeng, “Design and modeling of deep-submicrometer MOSFETs,” University
of California, Berkeley, CA, Electronics Research Laboratory Memorandum
No. UCB/ERL M90/90, 1990.
41. HSPICE User’s Manual, Meta Software, Campbell, CA, 1993.
42. Synopsys Inc., HSPICE User Guide: Simulation and Analysis, B-2008.09,
Synopsys Inc., September 2008.
43. J.H. Huang, Z.H. Liu, M.-C. Jeng, K. Hui, M. Chan, P.K. Ko, and C. Hu,
“BSIM3 manual—Version 2.0,” University of California, Berkeley, CA, 1994.
44. Y. Cheng, M. Chan, K. Hui, M.-C. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu,
P.K. Ko, and C. Hu, “BSIM3 version 3.0 user’s manual,” University of California,
Berkeley, CA, 1995.
45. Y. Cheng, M. Chan, K. Hui, M.-C. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, P.K. Ko,
and C. Hu “BSIM3 version 3.1 user’s manual,” University of California, Berkeley,
CA, Electronics Research Laboratory Memorandum No. UCB/ERL M97/2, 1997.
46. Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Ko, and C. Hu,
“A physical and scalable I–V in BSIMv3 for analog/digital simulation,” IEEE
Transactions on Electron Devices, vol. 44, no. 2, pp. 277–287, 1997.
47. Y. Cheng, T. Sugii, K. Chen, and C. Hu, “Modeling of small size MOSFETs with
reverse short channel and narrow width effects for circuit simulation,” SolidState Electronics, vol. 41, no, 9, pp. 1227–1231, 1997.
48. Si2. n.d. “Si2 (CMC) homepage.” https://www.si2.org/cmc_index.php, accessed
May 26, 2015.
49. C. Hu et al., “Description of the code changes in BSIM3v3.1 versus BSIM3v3.0,”
1997. http://www-device.eecs.berkeley.edu/bsim/?page=BSIM3_Arc, accessed
May 26, 2015.
50. W. Liu, X. Jin, and C. Hu, “BSIM3v3.2 Model enhancements and improvements
relative to BSIM3v3.1,” University of California, Berkeley, CA, 1998.
51. Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User’s Guide, Kluwer
Academic Publishers, London, 1999.
52. H. deGraaff and F. Klaassen, Compact Transistor Modeling for Circuit Design,
Springer-Verlag: Wein, Austria, 1990.
53. R.M.D.A. Velghe, D.B.M. Klaassen, and F.M. Klaassen, “Compact MOS modeling for analog circuit simulation,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 485–488, 1993.
References
34. H. Schichmann and D. Hodges, “Modeling and simulation of insulated-gate
field-effect transistor switching circuits,” IEEE Journal of Solid-State Circuits,
vol. 3, no. 3, pp. 285–289, 1968.
35. A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits
using SPICE2,” University of California, Berkeley, CA, Electronics Research
Laboratory Memorandum No. UCB/ERL M80/7, 1980.
36. R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bassous, and A.R.
LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256–268, 1974.
37. F. van de Wiele, “A long channel MOSFET model,” Solid-State Electronics, vol. 22,
no. 12, pp. 991–997, 1979.
38. C.C. McAndrew and J.J. Victory, “Accuracy of approximations in MOSFET charge
models,” IEEE Transactions on Electron Devices, vol. 49, no. 1, pp. 72–81, 2002.
39. S. Liu, “A unified CAD model for MOSFETs,” University of California, Berkeley,
CA, Electronics Research Laboratory Memorandum No. UCB/ERL M81/31, 1981.
40. M.C. Jeng, “Design and modeling of deep-submicrometer MOSFETs,” University
of California, Berkeley, CA, Electronics Research Laboratory Memorandum
No. UCB/ERL M90/90, 1990.
41. HSPICE User’s Manual, Meta Software, Campbell, CA, 1993.
42. Synopsys Inc., HSPICE User Guide: Simulation and Analysis, B-2008.09,
Synopsys Inc., September 2008.
43. J.H. Huang, Z.H. Liu, M.-C. Jeng, K. Hui, M. Chan, P.K. Ko, and C. Hu,
“BSIM3 manual—Version 2.0,” University of California, Berkeley, CA, 1994.
44. Y. Cheng, M. Chan, K. Hui, M.-C. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu,
P.K. Ko, and C. Hu, “BSIM3 version 3.0 user’s manual,” University of California,
Berkeley, CA, 1995.
45. Y. Cheng, M. Chan, K. Hui, M.-C. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, P.K. Ko,
and C. Hu “BSIM3 version 3.1 user’s manual,” University of California, Berkeley,
CA, Electronics Research Laboratory Memorandum No. UCB/ERL M97/2, 1997.
46. Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Ko, and C. Hu,
“A physical and scalable I–V in BSIMv3 for analog/digital simulation,” IEEE
Transactions on Electron Devices, vol. 44, no. 2, pp. 277–287, 1997.
47. Y. Cheng, T. Sugii, K. Chen, and C. Hu, “Modeling of small size MOSFETs with
reverse short channel and narrow width effects for circuit simulation,” SolidState Electronics, vol. 41, no, 9, pp. 1227–1231, 1997.
48. Si2. n.d. “Si2 (CMC) homepage.” https://www.si2.org/cmc_index.php, accessed
May 26, 2015.
49. C. Hu et al., “Description of the code changes in BSIM3v3.1 versus BSIM3v3.0,”
1997. http://www-device.eecs.berkeley.edu/bsim/?page=BSIM3_Arc, accessed
May 26, 2015.
50. W. Liu, X. Jin, and C. Hu, “BSIM3v3.2 Model enhancements and improvements
relative to BSIM3v3.1,” University of California, Berkeley, CA, 1998.
51. Y. Cheng and C. Hu, MOSFET Modeling and BSIM3 User’s Guide, Kluwer
Academic Publishers, London, 1999.
52. H. deGraaff and F. Klaassen, Compact Transistor Modeling for Circuit Design,
Springer-Verlag: Wein, Austria, 1990.
53. R.M.D.A. Velghe, D.B.M. Klaassen, and F.M. Klaassen, “Compact MOS modeling for analog circuit simulation,” in IEEE International Electron Devices Meeting
Technical Digest, pp. 485–488, 1993.