478
References
16. C.C. Enz, F. Krummenacher, and E.A. Vittoz, “An analytical MOS transistor
model valid in all regions of operation and dedicated to low voltage and lowcurrent applications,” Journal of Analog Integrated Circuit and Signal Processing,
vol. 8, no. 1, pp. 83–114, 1995.
17. M. Chan, K.Y. Hui, C. Hu, and P.K. Ko, “A robust and physical BSIM3 nonquasi-static transient and AC small signal model for circuit simulation,” IEEE
Transactions on Electron Devices, vol. 45, no. 4, pp. 834–841, 1998.
18. M. Miura-Mattausch, H. Ueno, M. Tanaka, H.J. Mattausch, S. Kamashiro,
T. Yamaguchi, K.Yamashita, and N. Nakayama, “HiSIM: A MOSFET
model for circuit simulation connecting device performance with technology,” IEEE International Electron Devices Meeting Technical Digest, pp. 109–112,
2002.
19. G. Gildenblat, X. Li, W. Wu, H. Wang, A. Jha, R. van Langevelde, G.D.J. Smit,
A.J. Scholten, and D.B.M. Klaassen, “PSP: An advanced surface-potential-based
MOSFET model for circuit simulation,” IEEE Transactions on Electron Devices,
vol. 53, no. 9, pp. 1979–1993, 2006.
20. Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor,
Oxford University Press, Oxford, 2010.
21. H.K.J. Ihantola and J.L. Moll, “Design theory of a surface field-effect transistor,”
Solid-State Electronics, vol. 7, no. 6, pp. 423–430, 1964.
22. H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9,
no. 10, pp. 927–937, 1966.
23. J.R. Brews, “A charge sheet model of the MOSFET,” Solid-State Electronics,
vol. 21, no. 2, pp. 345–355, 1978.
24. B.J. Sheu, D.L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley shortchannel IGFET model for MOS transistors,” IEEE Journal of Solid-State Circuits,
vol. 22, no. 4, pp. 558–556, 1987.
25. C.T. Sah, “Evolution of MOS transistor—Form conception to VLSI,” Proceedings
of IEEE, vol. 76, no. 10, pp. 1280–1326, 1988.
26. C.T. Sah, “Characteristics of the metal-oxide-semiconductor transistors,” IEEE
Transactions on Electron Devices, vol. 11, no. 7, pp. 324–345, 1964.
27. L.W. Nagel, “SPICE2—A computer program to simulate semiconductor circuits,” University of California, Berkeley, CA, Electronic Research Laboratory
Memo ERL-M250, 1975.
28. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
29. S. Saha, “Device characteristics of sub-20-nm silicon nanotransistors,” in Proceedings of the SPIE Conference on Design and Process Integration for Microelectronic
Manufacturing, vol. 5042, pp. 172–179, 2003.
30. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6344405, February 5, 2002.
31. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
32. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
33. H. Iwai, “CMOS technology—Year 2010 and beyond,” IEEE Journal of Solid-State
Circuits, vol. 34, no. 3, pp. 357–366, 1999.
References
16. C.C. Enz, F. Krummenacher, and E.A. Vittoz, “An analytical MOS transistor
model valid in all regions of operation and dedicated to low voltage and lowcurrent applications,” Journal of Analog Integrated Circuit and Signal Processing,
vol. 8, no. 1, pp. 83–114, 1995.
17. M. Chan, K.Y. Hui, C. Hu, and P.K. Ko, “A robust and physical BSIM3 nonquasi-static transient and AC small signal model for circuit simulation,” IEEE
Transactions on Electron Devices, vol. 45, no. 4, pp. 834–841, 1998.
18. M. Miura-Mattausch, H. Ueno, M. Tanaka, H.J. Mattausch, S. Kamashiro,
T. Yamaguchi, K.Yamashita, and N. Nakayama, “HiSIM: A MOSFET
model for circuit simulation connecting device performance with technology,” IEEE International Electron Devices Meeting Technical Digest, pp. 109–112,
2002.
19. G. Gildenblat, X. Li, W. Wu, H. Wang, A. Jha, R. van Langevelde, G.D.J. Smit,
A.J. Scholten, and D.B.M. Klaassen, “PSP: An advanced surface-potential-based
MOSFET model for circuit simulation,” IEEE Transactions on Electron Devices,
vol. 53, no. 9, pp. 1979–1993, 2006.
20. Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor,
Oxford University Press, Oxford, 2010.
21. H.K.J. Ihantola and J.L. Moll, “Design theory of a surface field-effect transistor,”
Solid-State Electronics, vol. 7, no. 6, pp. 423–430, 1964.
22. H.C. Pao and C.T. Sah, “Effects of diffusion current on characteristics of metaloxide (insulator)-semiconductor transistors,” Solid-State Electronics, vol. 9,
no. 10, pp. 927–937, 1966.
23. J.R. Brews, “A charge sheet model of the MOSFET,” Solid-State Electronics,
vol. 21, no. 2, pp. 345–355, 1978.
24. B.J. Sheu, D.L. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley shortchannel IGFET model for MOS transistors,” IEEE Journal of Solid-State Circuits,
vol. 22, no. 4, pp. 558–556, 1987.
25. C.T. Sah, “Evolution of MOS transistor—Form conception to VLSI,” Proceedings
of IEEE, vol. 76, no. 10, pp. 1280–1326, 1988.
26. C.T. Sah, “Characteristics of the metal-oxide-semiconductor transistors,” IEEE
Transactions on Electron Devices, vol. 11, no. 7, pp. 324–345, 1964.
27. L.W. Nagel, “SPICE2—A computer program to simulate semiconductor circuits,” University of California, Berkeley, CA, Electronic Research Laboratory
Memo ERL-M250, 1975.
28. K.J. Kuhn, “Considerations for ultimate CMOS scaling,” IEEE Transactions on
Electron Devices, vol. 59, no. 7, pp. 1813–1828, 2012.
29. S. Saha, “Device characteristics of sub-20-nm silicon nanotransistors,” in Proceedings of the SPIE Conference on Design and Process Integration for Microelectronic
Manufacturing, vol. 5042, pp. 172–179, 2003.
30. S.K. Saha, “Transistors having optimized source-drain structures and methods
for making the same,” US Patent 6344405, February 5, 2002.
31. S. Saha, “Design considerations for 25 nm MOSFET devices,” Solid-State
Electronics, vol. 45, no. 10, pp. 1851–1857, 2001.
32. S. Saha, “Scaling considerations for high performance 25 nm metal-oxidesemiconductor field-effect transistors,” Journal of Vacuum Science & Technology B,
vol. 19, no. 6, pp. 2240–2246, 2001.
33. H. Iwai, “CMOS technology—Year 2010 and beyond,” IEEE Journal of Solid-State
Circuits, vol. 34, no. 3, pp. 357–366, 1999.