477
References
Chapter 1
1. M.S. Lundstrom and D.A. Antonidis, “Compact models and the physics of
nanoscale FETs,” IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 225–233,
2014.
2. C.C. McAndrew, “Practical modeling for circuit simulation,” IEEE Journal of
Solid-State Circuits, vol. 33, no. 3, pp. 439–448, 1998.
3. J.S.C. Kilby, “Miniaturized electronics circuits,” US Patent 3138743, June 23,
1964.
4. Y.S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M.A.U. Karim, N. Paydavosi,
J.P. Duarte, C.C. Enz, A.M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Transactions on Electron Devices, vol. 61,
no. 2, pp. 234–244, 2014.
5. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
6. S.K. Saha, N.D. Arora, M.J. Deen, and M. Miura-Mattausch, “Advanced compact models and 45-nm modeling challenges,” IEEE Transactions on Electron
Devices, vol. 53, no. 9, pp. 1957–1960, 2006.
7. S.K. Saha, “Introduction to technology computer aided design,” in Technology
Computer Aided Design: Simulation for VLSI MOSFET, C.K. Sarkar (ed.). CRC
Press, Boca Raton, FL, 2013.
8. S.K. Saha, “Managing technology CAD for competitive advantage: An efficient
approach for integrated circuit fabrication technology development,” IEEE
Transactions on Engineering and Management, vol. 46, no. 2, pp. 221–229, 1999.
9. N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
10. S.K. Saha, M.J. Deen, and H. Masuda, “Compact interconnect models for
gigascale integration,” IEEE Transactions on Electron Devices, vol. 56, no. 9,
pp. 1784–1786, 2009.
11. W. Shockley, “Semiconductor amplifier,” US Patent 2502488, April 4, 1950.
12. J. Bardeen and W.H. Brattain, “Three-electrode circuit element utilizing semiconductor materials,” US Patent 2524035, October 3, 1950.
13. J.J. Ebers and J.L. Moll, “Large-signal behavior of junction transistors,”
Proceedings of IRE, vol. 42, no. 12, pp. 1761–1772, 1954.
14. H.K. Gummel and C.C. Poon, “An integral charge control model for bipolar
transistors,” Bell System Technical Journal, vol. 49, no. 5, pp. 827–852, 1970.
15. L. Nagel and D. Pederson, “Simulation program with integrated circuit emphasis,” University of California, Berkeley, CA, Electronics Research Laboratory
Memorandum No. UCB/ERL M352, 1973.
References
Chapter 1
1. M.S. Lundstrom and D.A. Antonidis, “Compact models and the physics of
nanoscale FETs,” IEEE Transactions on Electron Devices, vol. 61, no. 2, pp. 225–233,
2014.
2. C.C. McAndrew, “Practical modeling for circuit simulation,” IEEE Journal of
Solid-State Circuits, vol. 33, no. 3, pp. 439–448, 1998.
3. J.S.C. Kilby, “Miniaturized electronics circuits,” US Patent 3138743, June 23,
1964.
4. Y.S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M.A.U. Karim, N. Paydavosi,
J.P. Duarte, C.C. Enz, A.M. Niknejad, and C. Hu, “BSIM6: Analog and RF compact model for bulk MOSFET,” IEEE Transactions on Electron Devices, vol. 61,
no. 2, pp. 234–244, 2014.
5. S.K. Saha, “Modeling process variability in scaled CMOS technology,” IEEE
Design & Test of Computers, vol. 27, no. 2, pp. 8–16, 2010.
6. S.K. Saha, N.D. Arora, M.J. Deen, and M. Miura-Mattausch, “Advanced compact models and 45-nm modeling challenges,” IEEE Transactions on Electron
Devices, vol. 53, no. 9, pp. 1957–1960, 2006.
7. S.K. Saha, “Introduction to technology computer aided design,” in Technology
Computer Aided Design: Simulation for VLSI MOSFET, C.K. Sarkar (ed.). CRC
Press, Boca Raton, FL, 2013.
8. S.K. Saha, “Managing technology CAD for competitive advantage: An efficient
approach for integrated circuit fabrication technology development,” IEEE
Transactions on Engineering and Management, vol. 46, no. 2, pp. 221–229, 1999.
9. N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice,
Springer-Verlag, Wien, Austria, 1993.
10. S.K. Saha, M.J. Deen, and H. Masuda, “Compact interconnect models for
gigascale integration,” IEEE Transactions on Electron Devices, vol. 56, no. 9,
pp. 1784–1786, 2009.
11. W. Shockley, “Semiconductor amplifier,” US Patent 2502488, April 4, 1950.
12. J. Bardeen and W.H. Brattain, “Three-electrode circuit element utilizing semiconductor materials,” US Patent 2524035, October 3, 1950.
13. J.J. Ebers and J.L. Moll, “Large-signal behavior of junction transistors,”
Proceedings of IRE, vol. 42, no. 12, pp. 1761–1772, 1954.
14. H.K. Gummel and C.C. Poon, “An integral charge control model for bipolar
transistors,” Bell System Technical Journal, vol. 49, no. 5, pp. 827–852, 1970.
15. L. Nagel and D. Pederson, “Simulation program with integrated circuit emphasis,” University of California, Berkeley, CA, Electronics Research Laboratory
Memorandum No. UCB/ERL M352, 1973.