359
Beyond-CMOS Transistor Models: Tunnel FETs
Now, we define the threshold voltage V th of TFETs as the gate voltage V gs at
which the interband tunneling sets in at the source-channel junction [106].
In other words, V th is the value of the V gs at which the Fermi energy level E fp
in the p+ source region aligns with the conduction band energy level E cc in
the channel as shown in Figure 10.7b. Considering the i-channel region as
a conventional long channel MOSFET device, an inversion layer is formed at
V gs = V th0 , where V th0 is the long channel threshold voltage of the i-channel
MOSFET is given by (Equation 4.13)
V
V
th
fb
B
B
0
2
2
=
+
+
φ γ φ
(10.10)
where:
γ
ε
= 2
0
K qN C
si
b
o x and is defined in Equation 4.11
V fb is the flat band voltage
C ox is the oxide capacitance
N b is the carrier concentration in the i-channel region
φ B
k T
b
i
v
N n
=
(
)
ln
/ is the bulk potential defined in Equation 3.35
For an nTFET device with p+ source (electrons are minority carriers), the
injected number of minority carrier electrons from the source is insufficient
to maintain the channel inversion layer. Therefore, the MOSFET device is
in the off-state at V gs = V th0 . If we further increase the V gs beyond V th0 , the
channel-side conduction band E cc is pulled below the source-side valence
band E vp and the tunneling window ΔΦ is opened as shown in Figure 10.7b,
causing current flow.
We know that the Fermi level of the i-channel region is at the center of
the bandgap (E g /2), and for the degenerately doped p+ source region, we
can assume E vp ≈ E fs . Then at V gs = V th when the channel E cc is aligned with
source E vp = E fp , the energy required to pull down E cc from V gs = 0 to V gs = V th
is about E g /2. Therefore, the simplified expression for the threshold voltage
of an nTFET can be written as
V
V
E
q
thn
f b
B
B
g
=
+
+
+
2
2
2
φ γ φ
(10.11)
The same expression can be used for n-i-p structure with appropriate sign
convention for the i-region pMOSFET biasing condition. An expression for
V th for short channel TFET devices has also been reported to model V th rolloff [106]. However, experimental data show that the TFET device characteristics are independent of the length L of the intrinsic channel region for
L > L crit (~20 nm for silicon TFETs) [61,62]. Therefore, Equation 10.11 is valid for
threshold voltage modeling in most TFET devices. However, for L < L crit the
p-i-n diode leakage current influences V th , and therefore, appropriate channel
length dependence in V th must be used to account for the leakage currents in
the short channel devices with L < 20 nm.
Beyond-CMOS Transistor Models: Tunnel FETs
Now, we define the threshold voltage V th of TFETs as the gate voltage V gs at
which the interband tunneling sets in at the source-channel junction [106].
In other words, V th is the value of the V gs at which the Fermi energy level E fp
in the p+ source region aligns with the conduction band energy level E cc in
the channel as shown in Figure 10.7b. Considering the i-channel region as
a conventional long channel MOSFET device, an inversion layer is formed at
V gs = V th0 , where V th0 is the long channel threshold voltage of the i-channel
MOSFET is given by (Equation 4.13)
V
V
th
fb
B
B
0
2
2
=
+
+
φ γ φ
(10.10)
where:
γ
ε
= 2
0
K qN C
si
b
o x and is defined in Equation 4.11
V fb is the flat band voltage
C ox is the oxide capacitance
N b is the carrier concentration in the i-channel region
φ B
k T
b
i
v
N n
=
(
)
ln
/ is the bulk potential defined in Equation 3.35
For an nTFET device with p+ source (electrons are minority carriers), the
injected number of minority carrier electrons from the source is insufficient
to maintain the channel inversion layer. Therefore, the MOSFET device is
in the off-state at V gs = V th0 . If we further increase the V gs beyond V th0 , the
channel-side conduction band E cc is pulled below the source-side valence
band E vp and the tunneling window ΔΦ is opened as shown in Figure 10.7b,
causing current flow.
We know that the Fermi level of the i-channel region is at the center of
the bandgap (E g /2), and for the degenerately doped p+ source region, we
can assume E vp ≈ E fs . Then at V gs = V th when the channel E cc is aligned with
source E vp = E fp , the energy required to pull down E cc from V gs = 0 to V gs = V th
is about E g /2. Therefore, the simplified expression for the threshold voltage
of an nTFET can be written as
V
V
E
q
thn
f b
B
B
g
=
+
+
+
2
2
2
φ γ φ
(10.11)
The same expression can be used for n-i-p structure with appropriate sign
convention for the i-region pMOSFET biasing condition. An expression for
V th for short channel TFET devices has also been reported to model V th rolloff [106]. However, experimental data show that the TFET device characteristics are independent of the length L of the intrinsic channel region for
L > L crit (~20 nm for silicon TFETs) [61,62]. Therefore, Equation 10.11 is valid for
threshold voltage modeling in most TFET devices. However, for L < L crit the
p-i-n diode leakage current influences V th , and therefore, appropriate channel
length dependence in V th must be used to account for the leakage currents in
the short channel devices with L < 20 nm.