358
Compact Models for Integrated Circuit Design
CTFET technology and TFET-based IC chips, there has been a tremendous
interest in TFET-based exploratory novel circuit design [96,97]. However,
due to the lack of available compact TFET models for circuit CAD, lookup
tables or behavioral models are used for circuit analysis [98,99]. Recently,
a number of current and capacitance models for TFET devices have been
reported [100–107]. These reports include device models for multigate
TFETs [100,104,106,107] as well as for heterojunction nanowire TFETs.
Recently, Zhang et al. [103,107] reported a workable compact model and
coded it with Verilog-A for public use. However, a general-purpose compact TFET model for circuit simulation is not yet available. Therefore, the
underlying physical concepts to develop compact TFET models are presented in this section.
10.5.1 Threshold Voltage Model
Let us consider a p-i-n TFET device structure on an SOI substrate with heavily doped p+ source, intrinsic channel, and n+ drain regions as shown in
Figure 10.7a. The energy band diagram at the source-channel tunnel junction
of the device in the on-state is shown in Figure 10.7b. Since the p+ source
region is degenerately doped, the Fermi level E fp of the source-side tunneling
junction is assumed at or below the valence band E vp as shown in Figure 10.7b.
(a)
Gate
Oxide
Insulator
p+ Source
n+ Drain
i-Silicon
V s
V d
V g
t ox
t si
(b)
Electron
i-Silicon
On
ΔΦ
p+ Source
E cp
E g
E vp
E fp
E vc at On
E vc at V th
E cc at On
E cc at V th
V gs = V th
FIGURE 10.7
Threshold voltage modeling for TFETs: (a) 2D cross section of an ideal single gate p–i–n TFET
device structure with a p+ source, an i-silicon channel, and an n+ drain regions on an SOI
substrate; t ox and t si are the gate oxide thickness and body thickness, respectively; V s , V g , and
V d are the source, gate, and drain voltages, respectively and (b) energy band diagram of the
source-channel junction along the length of the device at the threshold condition (broken lines)
and on-state (solid lines).
Compact Models for Integrated Circuit Design
CTFET technology and TFET-based IC chips, there has been a tremendous
interest in TFET-based exploratory novel circuit design [96,97]. However,
due to the lack of available compact TFET models for circuit CAD, lookup
tables or behavioral models are used for circuit analysis [98,99]. Recently,
a number of current and capacitance models for TFET devices have been
reported [100–107]. These reports include device models for multigate
TFETs [100,104,106,107] as well as for heterojunction nanowire TFETs.
Recently, Zhang et al. [103,107] reported a workable compact model and
coded it with Verilog-A for public use. However, a general-purpose compact TFET model for circuit simulation is not yet available. Therefore, the
underlying physical concepts to develop compact TFET models are presented in this section.
10.5.1 Threshold Voltage Model
Let us consider a p-i-n TFET device structure on an SOI substrate with heavily doped p+ source, intrinsic channel, and n+ drain regions as shown in
Figure 10.7a. The energy band diagram at the source-channel tunnel junction
of the device in the on-state is shown in Figure 10.7b. Since the p+ source
region is degenerately doped, the Fermi level E fp of the source-side tunneling
junction is assumed at or below the valence band E vp as shown in Figure 10.7b.
(a)
Gate
Oxide
Insulator
p+ Source
n+ Drain
i-Silicon
V s
V d
V g
t ox
t si
(b)
Electron
i-Silicon
On
ΔΦ
p+ Source
E cp
E g
E vp
E fp
E vc at On
E vc at V th
E cc at On
E cc at V th
V gs = V th
FIGURE 10.7
Threshold voltage modeling for TFETs: (a) 2D cross section of an ideal single gate p–i–n TFET
device structure with a p+ source, an i-silicon channel, and an n+ drain regions on an SOI
substrate; t ox and t si are the gate oxide thickness and body thickness, respectively; V s , V g , and
V d are the source, gate, and drain voltages, respectively and (b) energy band diagram of the
source-channel junction along the length of the device at the threshold condition (broken lines)
and on-state (solid lines).