357
Beyond-CMOS Transistor Models: Tunnel FETs
As discussed earlier, though all-silicon TFETs offer very low I on than the
conventional MOSFETs, they have shown lowest I off with a small S. The current drivability in all-silicon TFETs can be improved by using high-k gate
dielectric, abrupt doping profile at the tunnel junction, a thinner body, higher
source doping, a double gate, a gate oxide aligned with the intrinsic region,
and a shorter i-region (and gate length) [41,76–78]. A recent study on sub-60
nm all-silicon TFET devices shows I on ~ 100 μA μm −1 [79].
In order to improve I on by low m r * materials tunneling junction, III–V
semiconductor-based TFETs are used in energy band engineering. The group
III–V materials provide small tunneling mass as well as different band-edge
alignments. Early experimental data on homojunction InGaAs p-i-n TFETs
show higher I on at a lower V gs than all-silicon TFETs. [80,81]. Though the
reported S is high, it is still above the thermal limit of MOSFETs [82]. The
effective E g can be further reduced by using III–V material-based hetrostructures with enhanced device performance compared to the homojunctions
[70–72,83–85]. In this context, the tunneling barrier can be reduced by using
InAs and GaAsSb for the source with AlGaSb and InGaAs for the channel.
The nanowire TFETs show a great potential for CTFET technology to
mitigate the risk of lattice mismatch and defective material growth in InAs
source and silicon channel pTFETs [70,86,87]. Experimental data on InAssilicon Esaki tunnel diodes show high tunneling current and well-defined
abrupt silicon-InAs heterojunction [87,88]. The vertical nanowire TFETs with
gate-all-around device architecture offers an optimal geometry for minimizing λ and best electrostatic control [89]. The fabricated vertical n-i-p InAs–Si–
Si nanowire heterojunction TFETs with InAs as a low E g source [90] show a
great promise for nanowire CTFETs.
CNT and graphene nanoribbons (GNR) are excellent choices for TFETs in
terms of device architecture and energy band engineering due to the light m r *
of their charge carriers, low and direct bandgap, and excellent electrostatic
control of the gate over the ultrathin body channel. The ongoing theoretical
and limited experimental studies show a great potential for carbon-based
TFETs [6,51,91–93]. However, for the practical implementation of GNR-TFETs,
a number of issues must be addressed including the influence of line edge
roughness on the bandgap and transport properties and their effects on
TFET device performance [94,95].
10.5 Compact TFET Models
From the discussions in Sections 10.3 and 10.4, it is found that CTFET technology is a viable candidate for beyond-CMOS technology due to its steepslope complementary devices with S < 60 mV per decade at low V gs , enabling
supply voltage scaling nearing 0.1 V [67]. For concurrent development of
Beyond-CMOS Transistor Models: Tunnel FETs
As discussed earlier, though all-silicon TFETs offer very low I on than the
conventional MOSFETs, they have shown lowest I off with a small S. The current drivability in all-silicon TFETs can be improved by using high-k gate
dielectric, abrupt doping profile at the tunnel junction, a thinner body, higher
source doping, a double gate, a gate oxide aligned with the intrinsic region,
and a shorter i-region (and gate length) [41,76–78]. A recent study on sub-60
nm all-silicon TFET devices shows I on ~ 100 μA μm −1 [79].
In order to improve I on by low m r * materials tunneling junction, III–V
semiconductor-based TFETs are used in energy band engineering. The group
III–V materials provide small tunneling mass as well as different band-edge
alignments. Early experimental data on homojunction InGaAs p-i-n TFETs
show higher I on at a lower V gs than all-silicon TFETs. [80,81]. Though the
reported S is high, it is still above the thermal limit of MOSFETs [82]. The
effective E g can be further reduced by using III–V material-based hetrostructures with enhanced device performance compared to the homojunctions
[70–72,83–85]. In this context, the tunneling barrier can be reduced by using
InAs and GaAsSb for the source with AlGaSb and InGaAs for the channel.
The nanowire TFETs show a great potential for CTFET technology to
mitigate the risk of lattice mismatch and defective material growth in InAs
source and silicon channel pTFETs [70,86,87]. Experimental data on InAssilicon Esaki tunnel diodes show high tunneling current and well-defined
abrupt silicon-InAs heterojunction [87,88]. The vertical nanowire TFETs with
gate-all-around device architecture offers an optimal geometry for minimizing λ and best electrostatic control [89]. The fabricated vertical n-i-p InAs–Si–
Si nanowire heterojunction TFETs with InAs as a low E g source [90] show a
great promise for nanowire CTFETs.
CNT and graphene nanoribbons (GNR) are excellent choices for TFETs in
terms of device architecture and energy band engineering due to the light m r *
of their charge carriers, low and direct bandgap, and excellent electrostatic
control of the gate over the ultrathin body channel. The ongoing theoretical
and limited experimental studies show a great potential for carbon-based
TFETs [6,51,91–93]. However, for the practical implementation of GNR-TFETs,
a number of issues must be addressed including the influence of line edge
roughness on the bandgap and transport properties and their effects on
TFET device performance [94,95].
10.5 Compact TFET Models
From the discussions in Sections 10.3 and 10.4, it is found that CTFET technology is a viable candidate for beyond-CMOS technology due to its steepslope complementary devices with S < 60 mV per decade at low V gs , enabling
supply voltage scaling nearing 0.1 V [67]. For concurrent development of