356
Compact Models for Integrated Circuit Design
order to realize a high I on and a steep slope, T(E) of the source tunneling barrier should be close to unity for a small change in V g . From Equation 10.2, it
is found that T(E) depends on λ, E g , and m*. Thus, high barrier transparency
(i.e., T(E) ~ 1) can be achieved by minimizing E g , m*, and λ. Now, E g and m*
depend on the materials of the TFET device structure, whereas λ depends
on the device architecture including geometry, doping profiles, and gate
capacitance [16,64,65]. Therefore, the performance of TFETs can be improved by
device architecture and energy band engineering, that is, using low-E g and lowm r * materials for forming the tunnel junction.
One way to improve TFET device performance by device architecture is to
minimize λ. A small λ offers a strong modulation of the channel energy bands
by the gate. This small value of λ, can be achieved by using a high-κ gate dielectric [57] with manufacturable ultrathin equivalent oxide thickness, ultrathin
body [49,64], and degenerately doped abrupt doping profile of the tunnel junction [65,66]. Another technique to improve I on by device architecture is to maximize the gate modulation of the tunneling barrier width by an appropriate
alignment of the tunneling path with the direction of the electric field modulated by the gate. By overlapping the gate with the tunneling region, or designing a source region covered with an epitaxial i-channel layer under the top gate,
I on can be improved by a factor of more than 10 along with a low S avg [19,67–69].
In addition to optimizing TFET device structure to improve device performance, the improvement in I on and S can be achieved by band engineering, that
is, use low-E g and low-effective mass m r * materials to increase interband tunneling. This is achieved by heterostructure TFETs with different source materials with respect to the channel and drain, creating staggered bandgap structures.
Device optimization should apply to both n- and p-type TFETs simultaneously,
to offer a complementary TFET (CTFET) technology for logic circuits.
In heterostructure TFETs, a low E g source material is used to reduce the
width of the energy barrier at the source junction in the on-state, whereas
a large E g drain material is used to create the largest possible width of the
energy barrier at the drain junction in the off-state to keep a low I off . The device
performance depends on the band’s lineup with each other at the heterojunction [5,70,71]. The reported data show that a combination of steep S and high
I on can be achieved with moderate doping and a staggered band lineup [72,73].
In a reported theoretical study on staggered bandgap structures, the CTFET
devices have been optimized by changing the source material from silicon to
low E g materials Ge and InAs for nTFETs and pTFETs, respectively [63]. The
numerical simulation data on 50 nm silicon channel length of Ge-source nTFETs
and InAs-source pTFETs show an improvement of I on by a factor of 480 and 162,
respectively, at V ds = V gs = 1 V over the identically designed all-silicon TFETs.
For example, the simulated Ge-source nTFETs and InAs-source pTFETs show
I on of 244 μA µm −1 and 83 mA µm −1 , respectively, with much lower I on /I off than
the comparable CMOS devices and S ~ 60 mV per decade of I ds [63]. Thus, the
heterostructure TFETs have a great potential to meet the target performance
objectives of CTFET technology operating at V dd << 0.5 V [70,71,74,75].
Compact Models for Integrated Circuit Design
order to realize a high I on and a steep slope, T(E) of the source tunneling barrier should be close to unity for a small change in V g . From Equation 10.2, it
is found that T(E) depends on λ, E g , and m*. Thus, high barrier transparency
(i.e., T(E) ~ 1) can be achieved by minimizing E g , m*, and λ. Now, E g and m*
depend on the materials of the TFET device structure, whereas λ depends
on the device architecture including geometry, doping profiles, and gate
capacitance [16,64,65]. Therefore, the performance of TFETs can be improved by
device architecture and energy band engineering, that is, using low-E g and lowm r * materials for forming the tunnel junction.
One way to improve TFET device performance by device architecture is to
minimize λ. A small λ offers a strong modulation of the channel energy bands
by the gate. This small value of λ, can be achieved by using a high-κ gate dielectric [57] with manufacturable ultrathin equivalent oxide thickness, ultrathin
body [49,64], and degenerately doped abrupt doping profile of the tunnel junction [65,66]. Another technique to improve I on by device architecture is to maximize the gate modulation of the tunneling barrier width by an appropriate
alignment of the tunneling path with the direction of the electric field modulated by the gate. By overlapping the gate with the tunneling region, or designing a source region covered with an epitaxial i-channel layer under the top gate,
I on can be improved by a factor of more than 10 along with a low S avg [19,67–69].
In addition to optimizing TFET device structure to improve device performance, the improvement in I on and S can be achieved by band engineering, that
is, use low-E g and low-effective mass m r * materials to increase interband tunneling. This is achieved by heterostructure TFETs with different source materials with respect to the channel and drain, creating staggered bandgap structures.
Device optimization should apply to both n- and p-type TFETs simultaneously,
to offer a complementary TFET (CTFET) technology for logic circuits.
In heterostructure TFETs, a low E g source material is used to reduce the
width of the energy barrier at the source junction in the on-state, whereas
a large E g drain material is used to create the largest possible width of the
energy barrier at the drain junction in the off-state to keep a low I off . The device
performance depends on the band’s lineup with each other at the heterojunction [5,70,71]. The reported data show that a combination of steep S and high
I on can be achieved with moderate doping and a staggered band lineup [72,73].
In a reported theoretical study on staggered bandgap structures, the CTFET
devices have been optimized by changing the source material from silicon to
low E g materials Ge and InAs for nTFETs and pTFETs, respectively [63]. The
numerical simulation data on 50 nm silicon channel length of Ge-source nTFETs
and InAs-source pTFETs show an improvement of I on by a factor of 480 and 162,
respectively, at V ds = V gs = 1 V over the identically designed all-silicon TFETs.
For example, the simulated Ge-source nTFETs and InAs-source pTFETs show
I on of 244 μA µm −1 and 83 mA µm −1 , respectively, with much lower I on /I off than
the comparable CMOS devices and S ~ 60 mV per decade of I ds [63]. Thus, the
heterostructure TFETs have a great potential to meet the target performance
objectives of CTFET technology operating at V dd << 0.5 V [70,71,74,75].