346
Compact Models for Integrated Circuit Design
tunneling between a bulk source and a two-dimensional (2D) surface channel.
This device structure is essentially a lateral TFET. The first known vertical TFET
has been reported by Leburton et al. [23] in 1988 in the design of a high-speed
transistor with the gate to control the negative differential resistance (NDR).
In 1992, Baba [24] independently proposed the lateral TFET device structure
similar to that reported by Quinn to use the gate of the transistor in controlling
NDR. This transistor has been referred to as the surface tunnel transistor (STT).
In the 1990s, the STTs fabricated in different semiconductor materials such as
gallium arsenide (GaAs), silicon-on-insulator (SOI), silicon (Si), and indium
gallium arsenide (InGaAs) have been widely studied to show NDR at room
temperature [25–33]. In this period, the focus of the STTs has been on field
control of the forward-biased characteristic of the Esaki tunnel junction and
in ways to utilize the NDR characteristics.
The interest on TFET as the potential device for beyond-CMOS technology
has grown since the reported gating of the reverse Zener tunneling current of
STTs to achieve better scaling due to the absence of punch-through by Reddick
and Amartunga in 1995 [34]. Subsequently, the gating of the Zener side of the
tunnel junction of a fabricated Si vertical TFET along with its potential for low
off-current (I off ) relative to the MOSFET has been reported by Hansch et al. in
2000 [35]. In 2004, the device characteristics of a lateral SOI TFET have been
reported by Aydin et al. [36], and low S in the TFET has been reported by
Wang et al. [4], Bhuwalka et al. [5], and Appenzeller et al. [6]. Theoretically, it
is shown that in a TFET, S < 60 mV per decade at room temperature [37,38].
However, less than 60-mV per decade S has been reported in only a few
TFETs based on carbon nanotubes (CNTs) [6,39], Si [40–43], germanium
(Ge) [44], and p+Ge/n+Si [45] channels. TFET device structure is constantly
evolving to outperform CMOS devices in comparable technology node [46].
10.3 Basic Theory of TFET Operation
10.3.1 Energy Band Diagram
The basic operating principle of a TFET can be understood from the energy
band diagram shown in Figure 10.2 of the ideal device structure, shown in
Figure 10.1. In Figure 10.2, the energy band diagram of a p–i–n TFET device
under various biasing conditions is shown with reference to the structure in Figure 10.1. Figure 10.2a shows that in the off-state with zero bias
(V gs = 0 = V ds ), the majority carriers in the channel as well as in the drain
regions see unsurmountable large potential barriers for tunneling and the
only current flow through the device is due to the reverse-biased leakage current of the p–i–n structure. When a positive gate bias (V gs > 0) is applied at the
gate, the source channel junction is reverse biased, and therefore, the energy
band of the channel region bends downward as shown in Figure 10.2b.
Compact Models for Integrated Circuit Design
tunneling between a bulk source and a two-dimensional (2D) surface channel.
This device structure is essentially a lateral TFET. The first known vertical TFET
has been reported by Leburton et al. [23] in 1988 in the design of a high-speed
transistor with the gate to control the negative differential resistance (NDR).
In 1992, Baba [24] independently proposed the lateral TFET device structure
similar to that reported by Quinn to use the gate of the transistor in controlling
NDR. This transistor has been referred to as the surface tunnel transistor (STT).
In the 1990s, the STTs fabricated in different semiconductor materials such as
gallium arsenide (GaAs), silicon-on-insulator (SOI), silicon (Si), and indium
gallium arsenide (InGaAs) have been widely studied to show NDR at room
temperature [25–33]. In this period, the focus of the STTs has been on field
control of the forward-biased characteristic of the Esaki tunnel junction and
in ways to utilize the NDR characteristics.
The interest on TFET as the potential device for beyond-CMOS technology
has grown since the reported gating of the reverse Zener tunneling current of
STTs to achieve better scaling due to the absence of punch-through by Reddick
and Amartunga in 1995 [34]. Subsequently, the gating of the Zener side of the
tunnel junction of a fabricated Si vertical TFET along with its potential for low
off-current (I off ) relative to the MOSFET has been reported by Hansch et al. in
2000 [35]. In 2004, the device characteristics of a lateral SOI TFET have been
reported by Aydin et al. [36], and low S in the TFET has been reported by
Wang et al. [4], Bhuwalka et al. [5], and Appenzeller et al. [6]. Theoretically, it
is shown that in a TFET, S < 60 mV per decade at room temperature [37,38].
However, less than 60-mV per decade S has been reported in only a few
TFETs based on carbon nanotubes (CNTs) [6,39], Si [40–43], germanium
(Ge) [44], and p+Ge/n+Si [45] channels. TFET device structure is constantly
evolving to outperform CMOS devices in comparable technology node [46].
10.3 Basic Theory of TFET Operation
10.3.1 Energy Band Diagram
The basic operating principle of a TFET can be understood from the energy
band diagram shown in Figure 10.2 of the ideal device structure, shown in
Figure 10.1. In Figure 10.2, the energy band diagram of a p–i–n TFET device
under various biasing conditions is shown with reference to the structure in Figure 10.1. Figure 10.2a shows that in the off-state with zero bias
(V gs = 0 = V ds ), the majority carriers in the channel as well as in the drain
regions see unsurmountable large potential barriers for tunneling and the
only current flow through the device is due to the reverse-biased leakage current of the p–i–n structure. When a positive gate bias (V gs > 0) is applied at the
gate, the source channel junction is reverse biased, and therefore, the energy
band of the channel region bends downward as shown in Figure 10.2b.