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Beyond-CMOS Transistor Models: Tunnel FETs
a typical TFET device includes an ultrathin body on the top of a buried oxide
layer, a gate electrode placed on the top of an ultrathin-gate dielectric, and a
heavily doped source region with doping type opposite to a heavily doped
drain region.
In principle, the same p-i-n TFET device structure shown in Figure 10.1 can
be used for n-type or p-type operation by appropriate biasing conditions. In
this respect, if a TFET is designed with symmetry between the n+ and p+
regions including similar doping levels, gate alignment, and geometries, the
device shows ambipolar behavior, that is, the transfer characteristics resemble
those of a pTFET when V gs < 0 and V ds < 0, and those of an nTFET when
V gs > 0 and V ds > 0. Thus, in principle, the TFET is an ambipolar device showing p-type behavior with dominant hole conduction and n-type behavior
with dominant electron conduction.
In another embodiment, a TFET can be used as a fully depleted channel
device [16]. In the case of a fully depleted channel TFET, the metal gate work
function of the gate is chosen to fully deplete the channel in the off-state. In
the on-state, the Zener tunneling is enabled [17]. In order to achieve high current density, abrupt doping profiles are required with degenerately doped
n+ and p+ regions [16].
One of the key challenges of TFET fabrication is that the gate must be selfaligned to the junction. If the gate is underlapped, that is, the junction is
moved outside the gate edge, the field control is degraded along with the
degradation of S. And, if the gate is overlapped, that is, the junction is under
the gate metal, the field in the on-condition depletes carriers on the source
side of the junction decreasing the tunneling injection. Thus, the gate must
be placed with a high precision approaching that of the lateral potential variation length, which is typically less than 10 nm [18] in these heavily doped
TFET structures.
Similar to MOSFETs, the gate control of the channel in TFETs can be improved
by using double-gate (DG) structures. In order to increase the on-current (I on ),
a degenerately doped pocket region can be used under the gate [19]. In addition to increasing I on , the pocket also offers lower S by aligning the gate field
with the internal tunnel junction field. TFET device structure is continuously
evolving with the development of process technology to minimize access
resistance, form abrupt degenerate junctions, self-align gate, and realize ultrathin channel.
A TFET-type device structure has been studied by Stuetzer [20] in 1952
predating Esaki’s discovery of pn-interband tunneling [21]. In this study, the
basic characteristics along with the ambipolar nature of the current–voltage
(I–V) characteristics have been reported in the field gating of a lateral germanium pn-junction. This study also shows the dependence of the transistor
characteristics on gate placement with respect to the pn-junction. In 1977,
Quinn et al. [22] designed a surface-channel MOS tunnel junction by replacing
the n+ source region of an nMOSFET device with a highly degenerate p+
source region to measure the sub-band splitting and transport properties of
Beyond-CMOS Transistor Models: Tunnel FETs
a typical TFET device includes an ultrathin body on the top of a buried oxide
layer, a gate electrode placed on the top of an ultrathin-gate dielectric, and a
heavily doped source region with doping type opposite to a heavily doped
drain region.
In principle, the same p-i-n TFET device structure shown in Figure 10.1 can
be used for n-type or p-type operation by appropriate biasing conditions. In
this respect, if a TFET is designed with symmetry between the n+ and p+
regions including similar doping levels, gate alignment, and geometries, the
device shows ambipolar behavior, that is, the transfer characteristics resemble
those of a pTFET when V gs < 0 and V ds < 0, and those of an nTFET when
V gs > 0 and V ds > 0. Thus, in principle, the TFET is an ambipolar device showing p-type behavior with dominant hole conduction and n-type behavior
with dominant electron conduction.
In another embodiment, a TFET can be used as a fully depleted channel
device [16]. In the case of a fully depleted channel TFET, the metal gate work
function of the gate is chosen to fully deplete the channel in the off-state. In
the on-state, the Zener tunneling is enabled [17]. In order to achieve high current density, abrupt doping profiles are required with degenerately doped
n+ and p+ regions [16].
One of the key challenges of TFET fabrication is that the gate must be selfaligned to the junction. If the gate is underlapped, that is, the junction is
moved outside the gate edge, the field control is degraded along with the
degradation of S. And, if the gate is overlapped, that is, the junction is under
the gate metal, the field in the on-condition depletes carriers on the source
side of the junction decreasing the tunneling injection. Thus, the gate must
be placed with a high precision approaching that of the lateral potential variation length, which is typically less than 10 nm [18] in these heavily doped
TFET structures.
Similar to MOSFETs, the gate control of the channel in TFETs can be improved
by using double-gate (DG) structures. In order to increase the on-current (I on ),
a degenerately doped pocket region can be used under the gate [19]. In addition to increasing I on , the pocket also offers lower S by aligning the gate field
with the internal tunnel junction field. TFET device structure is continuously
evolving with the development of process technology to minimize access
resistance, form abrupt degenerate junctions, self-align gate, and realize ultrathin channel.
A TFET-type device structure has been studied by Stuetzer [20] in 1952
predating Esaki’s discovery of pn-interband tunneling [21]. In this study, the
basic characteristics along with the ambipolar nature of the current–voltage
(I–V) characteristics have been reported in the field gating of a lateral germanium pn-junction. This study also shows the dependence of the transistor
characteristics on gate placement with respect to the pn-junction. In 1977,
Quinn et al. [22] designed a surface-channel MOS tunnel junction by replacing
the n+ source region of an nMOSFET device with a highly degenerate p+
source region to measure the sub-band splitting and transport properties of