344
Compact Models for Integrated Circuit Design
Therefore, in this chapter, an overview of the present state-of-the-art compact
modeling activities on TFETs is presented. First of all, the basic features of
TFET device structure are presented. Then the physics of TFET device operation is discussed. And, finally, the compact modeling activities on TFETs for
circuit CAD is presented. TFET as a green transistor has the potential to provide an acceptable device performance as the supply voltage approaches to
0.1 V beyond-CMOS devices.
10.2 Basic Features of TFETs
The most commonly referred TFETs are gated p-i-n diodes or gated p-n diodes
with an intrinsic channel as shown in Figure 10.1. In order to switch the device
on, the pn-junction is reverse biased and a voltage (V g ) is applied to the gate to
modulate the device characteristics. In order to be consistent with MOSFET
device technology, the names of the TFET device terminals are chosen such
that the biasing conditions for MOSFETs and TFETs are the same. Since a
reverse bias with V g > 0, V(n+) > 0, and V(p+) = 0 is needed across the p-i-n
structure to trigger tunneling similar to the biasing condition of an nMOSFET
with V g > 0, V d > 0, and V s = 0, the n+ region of a p-i-n TFET in Figure 10.1 is
referred to as its drain and p+ region as its source for an n-type TFET (nTFET).
Similarly, for a p-type TFET (pTFET), p+ region is referred to as the drain and
n+ region is the source to be consistent with biasing condition of a pMOSFET
device discussed in Chapters 4 and 5.
Thus, Figure 10.1 shows an nTFET device structure, with a heavily doped
p+ source region and a heavily doped n+ drain region. On the other hand,
in a pTFET, the source is doped with n+ and the drain is doped with p+. It is
observed from Figure 10.1 that a p-i-n TFET device structure is similar to that
of a conventional MOSFET except that the source is doped with the opposite dopant type with respect to the drain [4]. Thus, as shown in Figure 10.1,
Oxide
Gate
Insulator
V d
V s
V g
t si
t ox
n+ Drain
p+ Source
i-Silicon
FIGURE 10.1
2D cross section of an ideal single gate p–i–n TFET device structure with a p+ source, an intrinsic silicon (i-silicon) channel, and an n+ drain regions on an insulating substrate; t ox and t si are
the gate oxide thickness and body thickness, respectively; V s , V g , and V d are the source, gate,
and drain voltages, respectively.
Compact Models for Integrated Circuit Design
Therefore, in this chapter, an overview of the present state-of-the-art compact
modeling activities on TFETs is presented. First of all, the basic features of
TFET device structure are presented. Then the physics of TFET device operation is discussed. And, finally, the compact modeling activities on TFETs for
circuit CAD is presented. TFET as a green transistor has the potential to provide an acceptable device performance as the supply voltage approaches to
0.1 V beyond-CMOS devices.
10.2 Basic Features of TFETs
The most commonly referred TFETs are gated p-i-n diodes or gated p-n diodes
with an intrinsic channel as shown in Figure 10.1. In order to switch the device
on, the pn-junction is reverse biased and a voltage (V g ) is applied to the gate to
modulate the device characteristics. In order to be consistent with MOSFET
device technology, the names of the TFET device terminals are chosen such
that the biasing conditions for MOSFETs and TFETs are the same. Since a
reverse bias with V g > 0, V(n+) > 0, and V(p+) = 0 is needed across the p-i-n
structure to trigger tunneling similar to the biasing condition of an nMOSFET
with V g > 0, V d > 0, and V s = 0, the n+ region of a p-i-n TFET in Figure 10.1 is
referred to as its drain and p+ region as its source for an n-type TFET (nTFET).
Similarly, for a p-type TFET (pTFET), p+ region is referred to as the drain and
n+ region is the source to be consistent with biasing condition of a pMOSFET
device discussed in Chapters 4 and 5.
Thus, Figure 10.1 shows an nTFET device structure, with a heavily doped
p+ source region and a heavily doped n+ drain region. On the other hand,
in a pTFET, the source is doped with n+ and the drain is doped with p+. It is
observed from Figure 10.1 that a p-i-n TFET device structure is similar to that
of a conventional MOSFET except that the source is doped with the opposite dopant type with respect to the drain [4]. Thus, as shown in Figure 10.1,
Oxide
Gate
Insulator
V d
V s
V g
t si
t ox
n+ Drain
p+ Source
i-Silicon
FIGURE 10.1
2D cross section of an ideal single gate p–i–n TFET device structure with a p+ source, an intrinsic silicon (i-silicon) channel, and an n+ drain regions on an insulating substrate; t ox and t si are
the gate oxide thickness and body thickness, respectively; V s , V g , and V d are the source, gate,
and drain voltages, respectively.