336
Compact Models for Integrated Circuit Design
I
W
L
T
Q Q
v
v Q Q
ds
is
id
kT
s d
s s
kT
is
id
=
⋅
+
+
−
(
)+
−
(
)
µ
φ
φ
η
( )
,
,
2
1
1
(9.62)
The model has been extensively verified for a wide range of reliability and
scalability [83]
9.5 Dynamic Model
9.5.1 Common Multigate C–V Model
This section presents the dynamic model of the CMG DG-FETs for transient
analysis of the devices in circuit CAD. The intrinsic capacitance model that
describes the transient behavior of the transistors are derived from the terminal charges as described in Chapter 6.
For DG-FETs, the total charge in the body is given by the charges on the
top- and bottom-gate electrodes. The total charge is computed by integrating
the charge along the channel. Since the two gates are electrically interconnected, we have
Q
WC
V V
y dy
G
o x
g s
f b
L
=
−
−
⋅
∫
2
0
φ( )
(9.63)
where:
Q G denotes the charge on the electrically interconnected gate
The inversion charge in the body is divided between the source and the
drain terminals using Ward–Dutton charge partition approach discussed in
Chapter 6 [84,85]. The charge on source terminal (Q S ) is given by
Q
WC
y
L
V V
y
Q
C
dy
S
o x
g s
f b
b
ox
L
= −
−
−
−
−
⋅
∫
2
1
0
.
()
φ
(9.64)
Using charge conservation principle, the charge on the drain terminal (Q d )
can be expressed as
Q
WC
y
L
V V
y
Q
C
dy
D
o x
L
gs
fb
b
ox
= −
−
−
−
⋅
∫
2
0
φ( )
(9.65)
The surface potential as a function of the position y along the length of the
transistor, f s (y) is obtained using current continuity. Current continuity
states that the current is conserved along the length of the transistor.
Compact Models for Integrated Circuit Design
I
W
L
T
Q Q
v
v Q Q
ds
is
id
kT
s d
s s
kT
is
id
=
⋅
+
+
−
(
)+
−
(
)
µ
φ
φ
η
( )
,
,
2
1
1
(9.62)
The model has been extensively verified for a wide range of reliability and
scalability [83]
9.5 Dynamic Model
9.5.1 Common Multigate C–V Model
This section presents the dynamic model of the CMG DG-FETs for transient
analysis of the devices in circuit CAD. The intrinsic capacitance model that
describes the transient behavior of the transistors are derived from the terminal charges as described in Chapter 6.
For DG-FETs, the total charge in the body is given by the charges on the
top- and bottom-gate electrodes. The total charge is computed by integrating
the charge along the channel. Since the two gates are electrically interconnected, we have
Q
WC
V V
y dy
G
o x
g s
f b
L
=
−
−
⋅
∫
2
0
φ( )
(9.63)
where:
Q G denotes the charge on the electrically interconnected gate
The inversion charge in the body is divided between the source and the
drain terminals using Ward–Dutton charge partition approach discussed in
Chapter 6 [84,85]. The charge on source terminal (Q S ) is given by
Q
WC
y
L
V V
y
Q
C
dy
S
o x
g s
f b
b
ox
L
= −
−
−
−
−
⋅
∫
2
1
0
.
()
φ
(9.64)
Using charge conservation principle, the charge on the drain terminal (Q d )
can be expressed as
Q
WC
y
L
V V
y
Q
C
dy
D
o x
L
gs
fb
b
ox
= −
−
−
−
⋅
∫
2
0
φ( )
(9.65)
The surface potential as a function of the position y along the length of the
transistor, f s (y) is obtained using current continuity. Current continuity
states that the current is conserved along the length of the transistor.