330
Compact Models for Integrated Circuit Design
C DSC is the coupling capacitance between source/drain to channel, which
has similar L, λ, and V ds dependencies as ΔV th discussed earlier
The degradation in subthreshold swing is then modeled through a modification in v kT as
nv
C C
C
C
v
kT
d
I T
D SC
ox
kT
≡ +
+
+
1
(9.50)
where nv kT is substituted for v kT in all bias-dependent calculations.
9.3.2.2 Quantum Mechanical Effects
Quantum mechanical confinement of inversion carriers is well known in
bulk MOSFETs for a long time [13,75,76]. The large vertical electric field leads
to strong band bending at the surface and the inversion carriers are confined to dimensions along the length and width of the transistor as shown
in Figure 9.9a. This carrier confinement, also known as electrical confinement (EC), leads to splitting of energy bands into discrete sub-bands, which
reflects as an increase in the threshold voltage of the transistor and a decrease
in the gate capacitance, both of which act to reduce the current drive of the
transistor [13,61].
In the case of DG-FETs, unlike bulk FETs, there is strong carrier confinement
even at low electric fields, making the QME (quantum mechanical effect)
even more complex [77]. The carriers are bounded by gate insulator on two
sides, which is similar to carriers confined in a rectangular well [61,78–80].
0.03
0
0.0
0.2
0.4
3 0 n m
0.6
0.03
L (μm)
L (μm)
0.1
0.2
100 m
(a)
(b)
1.0 nm
200 m
ΔV
th (V)
ΔV
th (V)
300 m
400 m
T si = 20 nm, Na = 1e+15 cm
−3
V ds = 100 mV
T ox = 2 nm, Na = 1e+15 cm
−3
V ds = 100 mV
T ox = 1.0 nm
T ox = 1.5 nm
T ox = 2.0 nm
T ox = 2.5 nm
T ox = 3.0 nm
T si = 10 nm
T si = 15 nm
T si = 20 nm
T si = 25 nm
T si = 30 nm
0.1
0.2
FIGURE 9.8
Drain current model used to simulate SCE in lightly doped DG-nMOSFETs through threshold voltage roll-off for different: (a) oxide thickness and (b) body thickness; symbols represent TCAD and lines represent compact model (T t
si
fin
≡ ). (Data from M.V. Dunga et al., IEEE
Symposium on VLSI Technology, pp. 60–61, 2007.)
Compact Models for Integrated Circuit Design
C DSC is the coupling capacitance between source/drain to channel, which
has similar L, λ, and V ds dependencies as ΔV th discussed earlier
The degradation in subthreshold swing is then modeled through a modification in v kT as
nv
C C
C
C
v
kT
d
I T
D SC
ox
kT
≡ +
+
+
1
(9.50)
where nv kT is substituted for v kT in all bias-dependent calculations.
9.3.2.2 Quantum Mechanical Effects
Quantum mechanical confinement of inversion carriers is well known in
bulk MOSFETs for a long time [13,75,76]. The large vertical electric field leads
to strong band bending at the surface and the inversion carriers are confined to dimensions along the length and width of the transistor as shown
in Figure 9.9a. This carrier confinement, also known as electrical confinement (EC), leads to splitting of energy bands into discrete sub-bands, which
reflects as an increase in the threshold voltage of the transistor and a decrease
in the gate capacitance, both of which act to reduce the current drive of the
transistor [13,61].
In the case of DG-FETs, unlike bulk FETs, there is strong carrier confinement
even at low electric fields, making the QME (quantum mechanical effect)
even more complex [77]. The carriers are bounded by gate insulator on two
sides, which is similar to carriers confined in a rectangular well [61,78–80].
0.03
0
0.0
0.2
0.4
3 0 n m
0.6
0.03
L (μm)
L (μm)
0.1
0.2
100 m
(a)
(b)
1.0 nm
200 m
ΔV
th (V)
ΔV
th (V)
300 m
400 m
T si = 20 nm, Na = 1e+15 cm
−3
V ds = 100 mV
T ox = 2 nm, Na = 1e+15 cm
−3
V ds = 100 mV
T ox = 1.0 nm
T ox = 1.5 nm
T ox = 2.0 nm
T ox = 2.5 nm
T ox = 3.0 nm
T si = 10 nm
T si = 15 nm
T si = 20 nm
T si = 25 nm
T si = 30 nm
0.1
0.2
FIGURE 9.8
Drain current model used to simulate SCE in lightly doped DG-nMOSFETs through threshold voltage roll-off for different: (a) oxide thickness and (b) body thickness; symbols represent TCAD and lines represent compact model (T t
si
fin
≡ ). (Data from M.V. Dunga et al., IEEE
Symposium on VLSI Technology, pp. 60–61, 2007.)