322
Compact Models for Integrated Circuit Design
where:
V gs is the gate voltage
V fb is the flat-band voltage
Q s is the total charge in the body
C ox is the gate oxide capacitance per unit area, given by K ox ε 0 /T ox , with K ox
and T ox are the permittivity of oxide and oxide thickness, respectively
Then from Gauss’s law at the channel/oxide interface, we get
Q
K E
s
s i
x s
= – ε 0
(9.20)
where:
E xs is the vertical component of the electric field at the surface
Substituting Equation 9.20 in Equation 9.19, we get
V
V
y
K E
C
gs
fb
s
si
xs
ox
=
+
+
φ
ε
( )
0
(9.21)
Now, following the procedure to obtain E xs for bulk MOS (metal-oxidesemiconductor) capacitor system in Equation 3.51, we can show for a DG-FET
device
d
dx
d
dx
q
K
n
x y
V y
v
N
si
i
B
c h
kT
b
φ
ε
φ
φ
=
− −
+
2
0
2
exp
( , )
( )
d
dx
φ
(9.22)
We integrate Equation 9.22 from center potential f(x = 0, y) ≡ f 0 (y), df(x = 0, y)/
dx = 0 to any point f(x, y) and df(x, y)/dx to get
d
d
dx
qn
K
x y
V y
v
N
d dx
i
si
B
c h
kT
φ
ε
φ
φ
φ
=
− −
+
∫
2
0
0
2
exp
( , )
( )
b b
i
y
x y
n
d
∫
φ
φ
φ
0 ( )
( , )
(9.23)
After integration and simplification, we can express Equation 9.23 as
d x y
dx
qn
K
v
y
v
y
v
i
si
kT
s
kT
kT
φ
ε
φ
φ
( , )
exp
( ) exp
( )
=
−
2
0
0
2
⋅
− −
+
−
exp
( )
exp
( )
φ
φ
φ
φ
B
c h
kT
B
kT
V y
v
v
y
0 ( ( )
( )
y
E x E
s
x s
=
≡
2
2
(9.24)
where in Equation 9.24, we have used Equation 9.7 for N b /n i . Thus, the
vertical electric field at any point y along the surface of the channel is
given by
Compact Models for Integrated Circuit Design
where:
V gs is the gate voltage
V fb is the flat-band voltage
Q s is the total charge in the body
C ox is the gate oxide capacitance per unit area, given by K ox ε 0 /T ox , with K ox
and T ox are the permittivity of oxide and oxide thickness, respectively
Then from Gauss’s law at the channel/oxide interface, we get
Q
K E
s
s i
x s
= – ε 0
(9.20)
where:
E xs is the vertical component of the electric field at the surface
Substituting Equation 9.20 in Equation 9.19, we get
V
V
y
K E
C
gs
fb
s
si
xs
ox
=
+
+
φ
ε
( )
0
(9.21)
Now, following the procedure to obtain E xs for bulk MOS (metal-oxidesemiconductor) capacitor system in Equation 3.51, we can show for a DG-FET
device
d
dx
d
dx
q
K
n
x y
V y
v
N
si
i
B
c h
kT
b
φ
ε
φ
φ
=
− −
+
2
0
2
exp
( , )
( )
d
dx
φ
(9.22)
We integrate Equation 9.22 from center potential f(x = 0, y) ≡ f 0 (y), df(x = 0, y)/
dx = 0 to any point f(x, y) and df(x, y)/dx to get
d
d
dx
qn
K
x y
V y
v
N
d dx
i
si
B
c h
kT
φ
ε
φ
φ
φ
=
− −
+
∫
2
0
0
2
exp
( , )
( )
b b
i
y
x y
n
d
∫
φ
φ
φ
0 ( )
( , )
(9.23)
After integration and simplification, we can express Equation 9.23 as
d x y
dx
qn
K
v
y
v
y
v
i
si
kT
s
kT
kT
φ
ε
φ
φ
( , )
exp
( ) exp
( )
=
−
2
0
0
2
⋅
− −
+
−
exp
( )
exp
( )
φ
φ
φ
φ
B
c h
kT
B
kT
V y
v
v
y
0 ( ( )
( )
y
E x E
s
x s
=
≡
2
2
(9.24)
where in Equation 9.24, we have used Equation 9.7 for N b /n i . Thus, the
vertical electric field at any point y along the surface of the channel is
given by